An IC chip. The IC chip has an IC substrate, at least one IC functional layer on the substrate, and an etching hole that penetrates the IC functional layer from an outer side through to the substrate. A metal seal is arranged between a region of the IC functional layer and the etching hole.

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

A die stack structure is provided. The die stack structure includes a non-extended semiconductor die, an extended semiconductor die, and an extended top semiconductor die are stacked vertically over a base semiconductor die. The extended semiconductor die and the extended top semiconductor die each have an extension portion extending horizontally outward from one side thereof as compared to the non-extended semiconductor die. An encapsulant layer is formed over the base semiconductor die and encapsulates the sidewalls of the non-extended semiconductor die, the extended semiconductor die, and the extended top semiconductor die. Thermally conductive features are formed in the extension portion of the extended semiconductor die and in the extension portion of extended top semiconductor die. A thermally conductive structure is embedded in the encapsulant layer, extending vertically between the extended semiconductor die and the extended top semiconductor die, and contacting the thermally conductive features.