A method for manufacturing a dual-cavity structure and a dual-cavity structure, including: etching on a semiconductor substrate to form a first trench array, tops of the first trench array being separated from each other and bottoms thereof being communicated with each other to form a first cavity; growing a first epitaxial layer on the semiconductor substrate on which the first trench array is formed, to cover the first trench array by the first epitaxial layer; etching on the first epitaxial layer to form a second trench array; tops of the second trench array being separated from each other and bottoms thereof being communicated with each other to form a second cavity; growing a second epitaxial layer on the first epitaxial layer on which the second trench array is formed; and etching the first epitaxial layer and the second epitaxial layer to form a straight groove.

A MEMS device includes a substrate which has a first main surface and a second main surface facing the first main surface, and in which a silicon substrate, a silicon carbide layer having conductivity, and a silicon layer are sequentially stacked from a second main surface side toward a first main surface side, a cavity recessed over the silicon layer, the silicon carbide layer, and the silicon substrate from the first main surface of the substrate to the second main surface side of the substrate, a MEMS electrode which is arranged in the cavity, is composed of the silicon layer and the silicon carbide layer, and is spaced apart from a bottom surface of the cavity to the first main surface side, and an isolation joint which divides the MEMS electrode in a plan view and mechanically connects and electrically isolates both sides of the divided MEMS electrode.

A micromechanical pressure sensor device including a semiconductor base substrate of a first doping type on which an intermediate layer of the first doping type is situated, a cavity sealed by a sealing layer of a second doping type and including a reference pressure, a first grating of the second doping type, suspended inside the cavity on a buried connection region of the second doping type, the buried connection region laterally extending away from the cavity into the semiconductor base material, a second grating of the second doping type, situated on a side of the diaphragm region pointing to the cavity and suspended on the diaphragm region, the first grating and the second grating being electrically insulated from each other and forming a capacitance, a first connection electrically connected to the first grating via the buried connection region, and a second connection electrically connected to the second grating.

A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

A method for manufacturing a multi-layer MEMS component includes: providing a multi-layer substrate that has a monocrystalline carrier layer, a monocrystalline functional layer having a front side and a back side, and a bonding layer located between the back side and the carrier layer; growing a first polycrystalline layer over the front side of the monocrystalline functional layer; removing the monocrystalline carrier layer; and growing a second polycrystalline layer over the back side of the monocrystalline functional layer.

A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.

A semiconductor component. The semiconductor component has a semiconductor substrate, an insulation layer, and a first monocrystalline silicon layer. The insulation layer is arranged on the semiconductor substrate, and the first monocrystalline silicon layer is arranged on the insulation layer and at least one first region that extends starting from the first monocrystalline silicon layer up to a surface of the semiconductor substrate. The at least one first region includes second monocrystalline silicon.

A manufacturing method of micro-nano structure antireflective coating layer and a display apparatus thereof are described. The method includes providing a substrate, forming a silicon oxide layer on the substrate, forming a graphene layer with a hexagonal honeycomb lattice on the silicon oxide layer, and forming a bottom surface of the antireflective coating layer in the nucleation points by serving the graphene layer as a growing base layer, wherein a diffusion length and an atomic mass of diffusion atoms of the antireflective coating layer are decreased with time by a gradient growing manner to form a upper surface of the antireflective coating layer.

A method for manufacturing a multi-layer MEMS component includes: providing a multi-layer substrate that has a monocrystalline carrier layer, a monocrystalline functional layer having a front side and a back side, and a bonding layer located between the back side and the carrier layer; growing a first polycrystalline layer over the front side of the monocrystalline functional layer; removing the monocrystalline carrier layer; and growing a second polycrystalline layer over the back side of the monocrystalline functional layer.