At a motherboard for an image device, which is used for manufacturing an image device such as a liquid crystal device, an organic electroluminescence device, a mirror device, and an image-capturing device, a mark for alignment is provided on an outer side of a pixel area in which a plurality of pixels are arranged. In the photo-lithography process, a light exposure mask is arranged by using the mark as a reference position. For the mark, a recessed portion provided in a motherboard main body is filled with a filling film. The recessed portion includes a first groove extending along a first direction and a second groove extending along a second direction intersecting with the first direction, the second groove not intersecting with the first groove in plan view.

A position detection apparatus comprises an obtaining unit that obtains an image of a moiré that occurs due to first and second diffraction gratings overlapping; and a processor configured to perform a periodic analysis of a luminance distribution of the obtained image of the moiré, obtain a phase measurement value of the luminance distribution, and obtain a relative positioning between the first and second diffraction gratings, wherein the processor determines a phase shift amount for making the obtained phase measurement value be a value outside of a predetermined range including a discontinuous part of the phase, and performs a phase shift to shift the obtained phase measurement value by the determined phase shift amount, and obtains the relative positioning based on the phase-shifted phase measurement value.

A structure of a semiconductor device with a sub-segmented grating structure as a metrology mark and a method for configuring the metrology mark. The method for configuring a metrology mark may be used in a lithography process. The method may include determining an initial characteristic function of an initial metrology mark disposed within a layer stack. The method also includes perturbing one or more variables of the plurality of subsegments of the metrology mark (e.g., pitch, duty cycle, and/or line width of the plurality of subsegments) and further perturbing a thickness of one or more layers within the layer stack. The method further includes iteratively performing the perturbations until a minimized characteristic function of an initial metrology mark is determined to set a configuration for the plurality of subsegments.

According to one embodiment, a mark is a mark arranged on a substrate and including a line-and-space pattern having a substantially constant pitch on the substrate, the mark including: a first mark in which the line-and-space pattern extends in a direction at an angle that is less than 90° or greater than 90° with respect to the first direction, the first mark including a pair of first patterns arranged at a distance in a first direction along the substrate or a first periodic pattern having a period in the first direction; and a second mark in which the line-and-space pattern extends in a direction at an angle that is less than 90° or greater than 90° with respect to the second direction, the second mark including a pair of second patterns provided in correspondence with the pair of first patterns and arranged at a distance in a second direction along the substrate and intersecting the first direction or a second periodic pattern provided in correspondence with the first periodic pattern and having a period in the second direction.

The present invention provides a processing system that includes a first apparatus and a second apparatus, and processes a substrate, wherein the first apparatus includes a first measurement unit configured to detect a first structure and a second structure different from the first structure provided on the substrate, and measure a relative position between the first structure and the second structure, and the second apparatus includes an obtainment unit configured to obtain the relative position measured by the first measurement unit, a second measurement unit configured to detect the second structure and measure a position of the second structure, and a control unit configured to obtain a position of the first structure based on the relative position obtained by the obtainment unit and the position of the second structure measured by the second measurement unit.

A method of configuring a mark having a trench to be etched into a substrate, the method including: obtaining a relation between an extent of height variation across a surface of a probationary layer deposited on a probationary trench of a probationary depth and a thickness of the probationary layer; determining an extent of height variation across the surface of a layer deposited on the mark allowing a metrology system to determine a position of the mark; and configuring the mark by determining a depth of the trench based on the relation, the extent of height variation and the thickness of a process layer to be deposited on the mark.

The instant disclosure includes an alignment system. The alignment system includes a first set of alignment marks, a second set of alignment marks, and a third set of alignment marks. The first, second and third alignment marks correspondingly includes a plurality of segments separated into groups. Each of the group being symmetric to a respective other group. The third set of alignment marks are diagonal to the first set of alignment marks and the second set of alignment marks.

A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure at least includes two photolithography layers which are arranged in sequence and at least one blocking layer. Each photolithography layer includes a functional pattern and an overlay mark, and the photolithography layers include a first photolithography layer and a second photolithography layer. The first photolithography layer includes a first functional pattern and a first overlay mark, and the second photolithography layer includes a second functional pattern and a second overlay mark; and at least one blocking layer. The blocking layer is located between the first functional pattern and the second functional pattern, and a vertical distance between the first functional pattern and the second functional pattern is greater than a vertical distance between the first and second overlay marks, in a stacking direction of the photolithography layers.

The present disclosure relates to a semiconductor mark and a forming method thereof. The semiconductor mark comprises: a previous layer mark comprising first patterns and at least one second pattern, the second pattern being located between adjacent first patterns, the first pattern being different from the second pattern in material property. Since the first pattern and the second pattern in the previous layer mark in the semiconductor mark according to the present disclosure are different in material property, during measurement, the first pattern and the second pattern are different in reflectivity for measurement light. Thus, the contrast of images of the first pattern and the second pattern obtained during measurement is improved, the positions and boundaries of the first pattern and the second pattern are clearly determined, and the measurement of the previous layer mark is more accurate.

A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to first metal layer with a less than 40 nm alignment error; and a via disposed through the second level, where each of the second transistors includes a metal gate, and where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.