A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

The present document relates to a method of synchronizing devices, wherein each device operates in sync with an internal clock signal which is periodic to thereby define time cycles, at least one of the internal clock signals being periodic at a first frequency. The devices are mutually synchronized via a party line. The method comprises providing a system clock signal periodic at a second frequency smaller than the first frequency defining sequential system clock cycles; and synchronizing the internal clock signal with the system clock signal. At least one device triggers, in sync with the system clock signal, a system synchronization event comprising changing a signal status of a common party line signal on the party line and monitoring the common party line signal. The changing and monitoring are performed in sync with the system clock signal.

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Apparatus and method for specifying quantum operations such as qubit rotations in a quantum instruction. For example, one embodiment of an apparatus comprises: a quantum instruction processing pipeline to process a quantum instruction having one or more opcodes to specify quantum operations and one or more operands and/or fields to specify values to be used to perform the quantum operations; a quantum waveform synthesizer to synthesize a waveform to control a qubit based on the values specified by the operands and/or fields of the quantum instruction.

A sequence signal generator and a sequence signal generation method are provided. In the sequence signal generation method, a waveform output instruction sent by a host computer is received to acquire waveform data. The waveform data includes original square wave sequence data and target square wave sequence data, and the target square wave sequence data includes a preliminary delay parameter and a secondary delay parameter. An original square wave sequence signal is acquired according to the original square wave sequence data. According to the preliminary delay parameter, preliminary delay processing is performed on the original square wave sequence signal to acquire an intermediate square wave sequence signal, and according to the secondary delay parameter, secondary delay processing is performed on the intermediate square wave sequence signal to acquire a target square wave sequence signal.

A trigonometric function calculating device includes: an address generator that generates an address signal that is formed from plural bit strings and corresponds to a phase; a trigonometric function table that stores first sines and first cosines that respectively correspond to phases expressed by upper bits of the address signals, and second sines and a second cosines that respectively correspond to phases expressed by lower bits of the address signals; a calculation circuit that outputs, as a calculated value, a sine that corresponds to the address signal by calculating processing using the first sine, the first cosine, the second sine and the second cosine that correspond to the address signal and have been extracted by referring to the trigonometric function table; and a correcting section that corrects the calculated value on the basis of a correction value corresponding to the address signal.

An arbitrary waveform generator includes at least one analog output, a digital-to-analog converter connected to the analog output and a waveform source connected to the digital analog converter. The waveform source includes a waveform memory, a signal player and a signal processor. The waveform generator is controlled by a sequencer having an instruction memory for instructions and an instruction interpreter adapted to sequentially execute the instructions. A command table unit, in addition to the sequencer, is connected to the waveform source and includes a command table memory holding a plurality of commands. The commands include a waveform identifier for a waveform to be played and a parameter identifier describing how to modify the waveform in the signal processor. The sequencer can trigger the command table unit to execute a command therein, thereby playing the waveform with the parameter as identified by the command.

The present document relates to a method of synchronizing devices, wherein each device operates in sync with an internal clock signal which is periodic to thereby define time cycles, at least one of the internal clock signals being periodic at a first frequency. The devices are mutually synchronized via a party line. The method comprises providing a system clock signal periodic at a second frequency smaller than the first frequency defining sequential system clock cycles; and synchronizing the internal clock signal with the system clock signal. At least one device triggers, in sync with the system clock signal, a system synchronization event comprising changing a signal status of a common party line signal on the party line and monitoring the common party line signal. The changing and monitoring are performed in sync with the system clock signal.

A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.