Embodiments of the present invention provide a voltage protection apparatus (130, 160, 205, 630, 730), comprising an input (165, 210, 610, 710) to receive an input voltage provided to a processor (120), an output (190, 260, 680, 760) to output a throttle signal to the processor (120), a filter circuit (180, 240, 640, 660, 740) to filter the input voltage provided to the processor (120) to provide a filtered input voltage, and a first circuit (170, 230, 630, 650, 73) to compare the filtered input voltage to a first threshold voltage (175, 235, 635, 645, 735) and to cause the output (190, 260, 680, 760) to provide the throttle signal to the processor (120) indicative of the filtered input voltage dropping below the first threshold voltage.

An electronic device and a method of a power supply protection for a connection port are provided. The electronic device includes a first connection port with a first switch and a first controller and a first control circuit. The first controller determines a first preset value according to a state of the first switch activation signal correspondingly, and detects whether the first input voltage of the first connection port is greater than the first preset value. When the first input voltage is greater than the first preset value, the first controller enables a first abnormal signal on the first abnormal state detection pin. In response to a first forced closing signal being enabled, the first controller controls the first switch to disconnect both terminals.

A system can validate multiple nonvolatile random-access memory (NVRAM) devices in parallel. The system can concurrently write a first data to a first volatile memory of a first NVRAM device and a second NVRAM device. The system can modify a first electrical power source that provides an electrical power output that is received by the first NVRAM device and is received by the second NVRAM device to modify a voltage of the electrical power from a first value to a second value to initiate the first NVRAM device and the second NVRAM device to respectively perform a vault. The system can reset the first electrical power source, causing the first NVRAM device and the second NVRAM device to reset. The system can verify whether the first NVRAM device and the second NVRAM device respectively store the first data in volatile memory subsequent to performing the resetting.

Techniques are provided for detecting a fault across a pair of lines. Pulse power is applied across the pair of lines. The pulse power comprises alternating pulse on-time intervals and pulse off-time intervals. During a pulse off-time interval, a resistor is connected across the pair of lines and then disconnected when a voltage across the pair of lines reaches a first droop percentage in a first period of time. After disconnecting the resistor, it is determined whether the voltage across the pair of lines droops at least a second droop percentage within a second period of time that begins after the first period of time. Occurrence of a line-to-line fault across the pair of lines is determined when the voltage across the pair of lines droops by at least the second droop percentage or more within the second period of time.

A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.

A chip with power-glitch detection is provided, which includes a power terminal receiving power, an inverter, and a back-up power storage device coupled to the power terminal. The inverter has an input terminal coupled to the power terminal. The back-up power storage device transforms the power to back-up power. The inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the inverter.

Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

A protection circuit, and related method, for an electronic device including a first power output interface and a second power output interface is disclosed. The protection circuit includes a first switch element, coupled between a first voltage source and the first power output interface. The detection circuit being operation to detect an output voltage value of the second power output interface to generate a detection result. The first switch element, according to the detection result, connects the first voltage source to the first power output interface to allow the first power output interface to output power to an external terminal, or disconnects the first voltage source from the first power output interface.

The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

Embodiments relate to a system, program product, and method for mitigating voltage overshoot in one or more cores in a multicore processing device including a plurality of cores. The method includes determining, in real-time, an indication of power consumption within each core of the one or more cores. The method also includes determining, through the indication of power consumption, a voltage overshoot condition in the one or more cores. The method further includes increasing, for the one or more cores, a power demand thereof. The method also includes increasing, subject to the increasing the power demand, power delivery to the one or more cores, thereby at least arresting the rate of increase of the voltage overshoot.