Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

An information processing apparatus that detects a voice command via a microphone in order to activate the device and execute certain applications. The apparatus comprises a digital signal processor (DSP) and a host controller which are responsible for processing the voice commands. The DSP recognizes and processes voice commands intermittently while the host processor is in a sleep state, thereby reducing the overall power consumption of the apparatus. Further, when the DSP is configured to recognize voice commands intended, only to activate the device, a memory having a sufficiently lower storage capacity suffices.

In one example, a device to process analog sensor data is described. For example, a device may include at least one analog sensor to generate a first set of analog voltage signals and a crossbar array including a plurality of memristors. In one example, the crossbar array is to receive an input vector of the first set of analog voltage signals, generate an output vector comprising a second set of analog voltage signals that is based upon a dot product of the input vector and a matrix comprising resistance values of the plurality of memristors, detect a pattern of the output vector, and activate a processor upon a detection of the pattern.

The present invention provides a terminal control method, a protective case, and a terminal. In the method, a terminal may be disposed with two Hall effect sensors for sensing a change of a magnetic field generated by a magnet in a protective case, and identify a forward snap-fit operation, an opening operation, a backward snap-fit operation, and the like of the protective case. When detecting the forward snap-fit operation of the protective case, the terminal performs a screen off operation; or when detecting the backward snap-fit operation of the protective case, the terminal may skip performing screen off operation. In embodiments of the present invention, the protective case can be prevented from turning off a screen by mistake, so as to improve terminal control accuracy.

An electronic device is provided. The electronic device includes a display, an electronic pen, a slot in which the electronic pen can be inserted in or detached from, a pen sensing module configured to sense an insertion/detachment of the electronic pen, a pen input module configured to receive an input using the electronic pen, and a processor configured to activate the pen input module while the display maintains an OFF-state when the detachment of the electronic pen is sensed within the OFF-state of the display.

In some examples, an electronic device comprises a battery; a storage device storing a user profile, the user profile comprising a usage pattern of the battery; and a processor coupled to the battery and the storage device, the processor to: receive a battery measurement of the battery and operational data of a first component of the electronic device; calculate a battery consumption of the first component based on the battery measurement; compare the battery consumption to the usage pattern; update, based on the comparison, the user profile using a time series model, wherein inputs to the time series model include the battery measurement and the operational data; and adjust a battery consumption of the electronic device based on the updated user profile.

In some examples, an electronic device comprises a battery; a storage device storing a user profile, the user profile comprising a usage pattern of the battery; and a processor coupled to the battery and the storage device, the processor to: receive a battery measurement of the battery and operational data of a first component of the electronic device; calculate a battery consumption of the first component based on the battery measurement; compare the battery consumption to the usage pattern; update, based on the comparison, the user profile using a time series model, wherein inputs to the time series model include the battery measurement and the operational data; and adjust a battery consumption of the electronic device based on the updated user profile.

A computer may be provided on a mining machine comprising a mother board, a power supply in operable communication with the mother board, an input/output interface in communication with the mother board, and a plurality of hash boards each in communication with the mother board and comprising a plurality of mining chips. The computer may execute instructions that cause the computer to perform establishing communication with an external device, retrieving at least one profit variable from the external device, calculating an estimated profitability of a first mining chip based on the profit variable, and adjusting a chip voltage supplied to the first mining chip and adjusting a chip frequency of the first mining chip to maximize the estimated profitability. Alternatively, the instructions may cause the computer to adjust the chip voltage and the chip frequency to maintain a temperature within a predetermined range.