A data transmission method is provided, the method is applied to a wearable apparatus configured with a first operation system and a second operation system, and a power consumption of the first operation system is lower than a power consumption of the second operation system; the method; the method includes: obtaining a type of data to be transmitted; detecting current screen state information of the wearable apparatus; and determining target data according to the current screen state information of the wearable apparatus and the type of data to be transmitted, and transmitting the target data from the first operation system of the wearable apparatus to the second operation system of the wearable apparatus.

An energy offloading system is in direct electric communication with an energy supply and dynamically receives energy from the energy supply. The energy offloading system uses energy for high-load computations. The energy offloading system includes computers performing the high-load computations as well as servers, cooling units, and communication devices. When the energy from the energy supply is terminated, the energy offloading system may power down these and other devices, or may switch these devices to an alternative power source. The energy offloading system may be portable.

An energy offloading system is in direct electric communication with an energy supply and dynamically receives energy from the energy supply. The energy offloading system uses energy for high-load computations. The energy offloading system includes computers performing the high-load computations as well as servers, cooling units, and communication devices. When the energy from the energy supply is terminated, the energy offloading system may power down these and other devices, or may switch these devices to an alternative power source. The energy offloading system may be portable.

Methods and systems for providing hardware compute resiliency by using a compute fabric that includes sensors and re-programmable data processing components.

Methods and systems for providing hardware compute resiliency by using a compute fabric that includes sensors and re-programmable data processing components.

According to an example aspect of the present invention, there is provided an apparatus comprising a first processing core configured to generate first control signals and to control a display by providing the first control signals to the display via a first display interface, a second processing core configured to generate second control signals and to control the display by providing the second control signals to the display via a second display interface, and the first processing core being further configured to cause the second processing core to enter and leave a hibernation state based at least partly on a determination, by the first processing core, concerning an instruction from outside the apparatus.

According to an example aspect of the present invention, there is provided an apparatus comprising a first processing core configured to generate first control signals and to control a display by providing the first control signals to the display via a first display interface, a second processing core configured to generate second control signals and to control the display by providing the second control signals to the display via a second display interface, and the first processing core being further configured to cause the second processing core to enter and leave a hibernation state based at least partly on a determination, by the first processing core, concerning an instruction from outside the apparatus.

A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling. The hint indicates the given core based on a relative prioritization of the first core type and the second core type.

Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling. The hint indicates the given core based on a relative prioritization of the first core type and the second core type.