A processor includes a communicating unit, a receiving unit, a processing unit, and a power-off controller. The receiving unit receives an operation from a user. The processing unit executes processing according to a processing request received by at least one of the communicating unit and the receiving unit. If a power-off request is received from a terminal by the communicating unit, the power-off controller stops the processing unit and disconnects a power supply when the operation received from the user by the receiving unit is not being processed and a condition determined in accordance with a processing mode of the power-off request is satisfied.

A device for electrically stimulating one or more anatomical target sites in a patient and for use in the treatment of a plurality of biological conditions of the patient. The device has a pulse generator providing electrical stimulation to the anatomical target sites; a power source for powering the pulse generator; stimulator electrodes connected to the pulse generator for stimulating the anatomical target sites; one or more optional sensing electrodes for monitoring physiological parameters with reference to the anatomical target sites; and a microprocessor programmed to vary a plurality of therapy protocol parameters governing the electrical stimulation to thereby modify operational life parameters of the power source.

A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus 2. The mapping parameters may be fixed or software programmable.

Systems and methods of adaptive thermal control are provided for information handling system platforms that may be implemented to automate and scale fan control settings by making the fan control settings relative to a reported component thermal control parameter value from a component of an information handling system platform, such as a CPU or other heat generating component. In one example, bounds for system use of vendor or component manufacturer-reported thermal control parameter values may be set for system cooling so as to confine use of these values within information handling system platform limits characterized by a manufacturer of an information handling system platform.

Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.

According to some examples, systems and methods are provided for determining a set of power states supported by a data storage device and applying an operation to the data storage device based on whether the set of power states includes a low power state.

An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.

In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.