An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.

A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

A method of debugging an applet, an electronic device, a storage medium. The method includes: selecting at least one debugging module from a plurality of debugging modules as a target debugging module according to a first debugging instruction; running the applet so that the target debugging module is interrupted in response to running to the target debugging module in the applet; and awakening the interrupted target debugging module for debugging according to a second debugging instruction, so as to generate a debugging result.

A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.

Described are computer-implementable method, system and computer-readable storage medium for supervised graph-based model for prediction of program failure using program log files. Using log file from a running program application, a log file graph is created. Node-level labels are adding to the log file graph, where the labels include an indication of first failure. The node-level labeled log file graph is processed by a graph neural network (GNN) and predictions are provided as to program cause of failure or first failure indication of other log file graphs based on the GNN processed node-level labeled log file graph.

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that use parallel hardware execution with software co-simulation to enable more advanced debugging operations on data flow architectures. Upon a halt to execution of a program thread, a state of the tiles that are executing the thread are saved and offloaded from the HTF to a host system. A developer may then examine this state on the host system to debug their program. Additionally, the state may be loaded into a software simulator that simulates the HTF hardware. This simulator allows for the developer to step through the code and to examine values to find bugs.

An information processing system is provided. The information processing system generates a program so as to output a hash value calculated based on a hash value calculation instruction included in a source code for generating the program, determines a set of analysis support information associated with the hash value calculation instruction and the hash value calculated based on the hash value calculation instruction, stores the set of the analysis support information and the hash value, stores at least a part of one or more hash values output as a result of execution of the program, and outputs, by using at least the part of the stored hash value, the analysis support information that makes the set with the hash value.

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

A security processor includes a key generator circuit configured to randomly generate a key, an encryption circuit configured to encrypt user data based on the key, and a security manager circuit configured to receive a first user identification (ID), which uniquely corresponds to a user of a device, and determine whether to allow access to the user data by authenticating the first user ID.