Apparatuses, systems, and techniques to manage memory arrays. In at least one embodiment an application programming interface (API) is performed to disassociate a virtual address indicated by the API from a corresponding physical address.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to add one or more entries to a log file system (LFS) invalidation table and scan the LFS invalidation table during a storage optimization operation. Each entry of the one or more entries maps a new valid logical block address (LBA) to an old invalidated LBA. The new valid LBA is updated version of the old invalidated LBA. The storage optimization operation includes moving data from a first location to a second location.

A method for extending a blockchain comprises, at a space server: allocating an amount of drive storage for generating proofs-of-space; or accessing a first challenge based on a prior block of the blockchain, the prior block comprising a first proof-of-space and a first proof-of-time; in response to accessing the first challenge, generating a second proof-of-space based on the first challenge and the amount of drive storage, the second proof-of-space indicating allocation of the amount of drive storage; accessing a second proof-of-time based on the prior block and indicating a first time delay elapsed after extension of the blockchain with the prior block; generating a new block comprising the second proof-of-space and the second proof-of-time; and broadcasting the new block over a distributed network.

A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.

Some embodiments of the present disclosure provide an associatively indexed circular buffer (ACB). The ACB may be viewed as a dynamically allocatable memory structure that offers in-order data access (say, first-in-first-out, or “FIFO”) or random order data access at a fixed, relatively low latency. The ACB includes a data store of non-contiguous storage. To manage the pushing of data to, and popping data from, the data store, the ACB includes a contiguous pointer generator, a content addressable memory (CAM) and a free pool.

A heterogeneous memory system is implemented using a low-latency near memory (NM) and a high-latency far memory (FM). Pages in the memory system include NM blocks stored in the NM and FM blocks stored in the FM. A page is assigned to a region in the memory system based on the proportion of NM blocks in the page. When accessing a block, the block address is used to determine a region of the memory system, and a block offset is used to determine whether the block is stored in NM or FM. The memory system may observe memory accesses to determine the access statistics of the page and the block. Based on a page's hotness and access density, the page may be migrated to a different region. Based on a block's hotness, the block may be migrated between NM and FM allocated to the page.

A memory access method and a computer system are provided. According to the memory access method, whether to flip the to-be-stored data for storage may be determined based on quantities of “1” and “0” in data to be written into a dynamic random access memory (DRAM) and a storage mode of the DRAM, to reduce a quantity of storage cells with high electric charges in the DRAM, thereby reducing a data error probability.

A processor may implement position-independent memory addressing by providing load and store instructions that include position-independent addressing modes. A memory address may contain a normalized pointer, where the memory address stores a normalized memory address that, when added to an offset previously determined for memory address, defines another memory address. The position-independent addressing mode may also support invalid memory addresses using a reserved value, where a load instruction providing the position-independent addressing mode may return a NULL value or generate an exception when determining that the stored normalized memory address is equal to the reserved value and where a store instruction providing the position-independent addressing mode may store the reserved value when determining that the memory address is an invalid or NULL memory address.

Technologies disclosed herein provide cryptographic computing with cryptographically encoded pointers in multi-tenant environments. An example method comprises executing, by a trusted runtime, first instructions to generate a first address key for a private memory region in the memory and generate a first cryptographically encoded pointer to the private memory region in the memory. Generating the first cryptographically encoded pointer includes storing first context information associated with the private memory region in first bits of the first cryptographically encoded pointer and performing a cryptographic algorithm on a slice of a first linear address of the private memory region based, at least in part, on the first address key and a first tweak, the first tweak including the first context information. The method further includes permitting a first tenant in the multi-tenant environment to access the first address key and the first cryptographically encoded pointer to the private memory region.

A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.