A parsing method includes the following: during parsing target bank, performing a row hammer operation on a logical row in target bank to determine a physical position relationship of the logical row; repeatedly performing the operation of performing the row hammer operation on the logical row in target bank to determine the physical position relationship of the logical row until all logical rows have been parsed; and determining a mapping relationship used for recording physical position relationships of multiple logical rows according to a linked list; where performing the row hammer operation on the logical row in target bank includes: acquiring a to-be-parsed logical row in target bank including multiple logical rows; performing the row hammer operation on the to-be-parsed logical row until at least one flipped logical row is obtained; and writing the at least one flipped logical row into the linked list.

A method and apparatus for allocating a memory address in a resource-centric network are disclosed. The method of allocating a memory address may include receiving a request for a new service, determining whether the new service is able to be accommodated in a virtual memory that is pre-allocated in a resource-centric network, when the new service is able to be accommodated, allocating a memory area for accommodating the new service to the virtual memory, and when the new service is not able to be accommodated, allocating the memory area by using an additionally allocated area of a virtual memory of the resource-centric network.

The embodiments of the disclosed technology relate to a controller and operating method thereof. Based on some embodiments of the disclosed technology, the controller may include i) a first memory configured to store map data including a plurality of map data entries, ii) a second memory configured to store map search data indicating a first map data entry, which corresponds to a first logical address, among the plurality of map data entries, and iii) a core configured to search for information on a physical address mapped to a second logical address from the map data, based on whether the map search data is stored in the second memory.

A cache includes a p-by-q array of memory units; a row addressing unit; and a column addressing unit. Each memory unit has an m-by-n array of memory cells. The column addressing unit has, for each memory unit, m n-to-one multiplexers, one associated with each of the m rows of the memory unit, wherein each n-to-one multiplexer has an input coupled to each of the n memory cells associated with the row associated with that multiplexer. The row addressing unit has, for each memory unit, n m-to-one multiplexers, one associated with each of the n columns of the memory unit, wherein each m-to-one multiplexer has an input coupled to each of the m memory cells associated with the column associated with that multiplexer. The row addressing unit and column addressing unit support reading and/or writing of the array of memory units, e.g. using virtual or physical addresses.

A system and an operating method thereof include a system on chip (SOC) flash controller having at least one SOC channel; at least one memory device coupled with the at least one SOC channel; a printed circuit board (PCB), wherein the SOC flash controller and the at least one memory device are mounted thereon; a flash address translation (FTL) address translator automatically managing the at least one memory device in accordance with a PCB board configuration file of the PCB board and a drive configuration file of the at least one memory device; and a fuse storing an open data plane (ODP) fuse setting generated in accordance with at least in part with data of the PCB board configuration file and the drive configuration file.

A method for providing input data for a layer of a convolutional neural network “CNN”, the method comprising: receiving input data comprising input data values to be processed in a layer of the CNN; determining addresses in banked memory of a buffer in which the received data values are to be stored based upon format data indicating a format parameter of the input data in the layer and indicating a format parameter of a filter which is to be used to process the input data in the layer; and storing the received input data values at the determined addresses in the buffer for retrieval for processing in the layer.

According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.

An apparatus for auto addressing includes a communication bus interface configured to receive an address assignment request to assign an address to the apparatus. A functional connection is configured to activate a device connected to the apparatus. A detector is configured to measure a characteristic of the device and to compare the characteristic with a validation parameter. The characteristic depends on the functional connection. An address assignment circuit is configured to store the address in a memory of the apparatus in response to receiving the address assignment request at the apparatus, and the characteristic being validated with the validation parameter.

In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.