The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.

Methods, systems, and apparatuses for unlocking a persistent region in memory are disclosed. An information handling apparatus includes a controller, a memory coupled to the controller, the memory having a persistent region that can either be locked or unlocked, and a firmware configured to determine whether the persistent region of the memory is locked, obtain a stored passphrase from a storage device if the persistent region is locked, and use the passphrase to unlock the persistent region of the memory.

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Technologies for addressing individual bits in memory include a device having a memory that includes partitions that each have tiles, in which each tile stores an individual bit. The device also includes circuitry to receive a request to access (e.g., read or write) a sequence of bits in a partition. The request specifies a logical row or column address. A corresponding tile is determined from the logical row or column address and for each bit in the sequence. The corresponding tile is accessed to read or write the bit therein.

Technologies for addressing individual bits in memory include a device having a memory that includes partitions that each have tiles, in which each tile stores an individual bit. The device also includes circuitry to receive a request to access (e.g., read or write) a sequence of bits in a partition. The request specifies a logical row or column address. A corresponding tile is determined from the logical row or column address and for each bit in the sequence. The corresponding tile is accessed to read or write the bit therein.

Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.

The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

A mobile device (100) includes a processing device (140), a random access memory, RAM, (150) and an embedded mass storage device (160). A first interface (IF1) is provided between the processing device (140) and the RAM (150). The first interface (IF1) supports access of the processing device (140) to the RAM (150). The mass storage device (160) includes a controller (170) and a non-volatile flash memory (180). A second interface (IF2) is provided between the controller (170) and the flash memory (180). The second interface (IF2) supports access of the controller (170) to the flash memory (180). A third interface (IF3) is provided between the controller (170) and the processing device (140). The third interface (IF3) supports access of the controller (170) to the RAM (150).

Example implementations disclosed herein include techniques for a ready only bufferpool for use in local nodes of a multi-node computing system. Read only transactions executed by a processor can reference a ready only bufferpool resident in a VRAM on the same node. If the desired data page is in the bufferpool the transaction can immediately read data records from the cached data pages. If the desired data page is not in the bufferpool, then the transaction can cause a copy of a corresponding data page in a secondary memory to be installed in the bufferpool. The bufferpool can include more than one copy of a data page simultaneously to handle and prevent cache line misses. Data page are dropped from the bufferpool based on an incrementing per data page counter.

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Writing time is shortened even in a memory writing time for each access unit is not constant. A writing time prediction information holding unit holds writing time prediction information for predicting the writing time in a plurality of memory modules for each of a plurality of memory modules. A request selecting unit preferentially selects a write request of which longer writing time is predicted out of a plurality of write requests requiring writing in each of a plurality of memory modules on the basis of the writing time prediction information.