A controller according to an embodiment includes a memory and a processor. The processor controls an external control target device. The processor includes a controller-function core and a computer-function core. The controller-function core executes a ladder application that reads out I/O data received from the control target device from an I/O memory out of a storage area of the memory, stores a part of the I/O data out of the read I/O data in a shared memory different from the I/O memory out of the storage area, and stores control data to be transmitted to the control target device in the I/O memory. The computer-function core is a core different from the controller-function core and executes a computer application that reads out the I/O data from the shared memory.

A secure semiconductor chip is presented. The semiconductor chip is, for example, a system-on-chip. Processor cores included in the system-on-chip are connected to normal IPs through a system bus. A secure bus, which is a hidden bus physically separated from the system bus, is provided separately. The secure bus is connected to security IPs which perform security functions or handle security data. The secure semiconductor chip may perform necessary authentication by switching a normal mode to a secure mode.

According to the disclosure, it is possible to perform comparison with high accuracy even if a deviation in the time axis direction occurs between the target signal and the comparison condition. A control apparatus includes an acquisition part acquiring a time series signal output from a device; a comparison condition storage part storing information indicating a temporal change of a predetermined comparison condition; an area determination part determining a target area, which is an area satisfying a predetermined condition indicating that change of a value is stable, in the signal acquired by the acquisition part; and a comparison part performing comparison with the comparison condition by using a signal of the target area determined by the area determination part.

Disclosed is a secure semiconductor chip. The semiconductor chip is, for example, a system-on-chip. The system-on-chip is operated by connecting normal IPs to a processor core included therein via a system bus. A secure bus, which is a hidden bus physically separated from the system bus, is separately provided. Security IPs for performing a security function or handling security data are connected to the secure bus. The secure semiconductor chip can perform required authentication while shifting between a normal mode and a secure mode.

Disclosed is a secure semiconductor chip. When a physical attack such as a depackaging attack occurs, the semiconductor chip can detect the physical attack. A semiconductor chip according to one embodiment comprises an energy harvesting element inside a package. The energy harvesting element may comprise, for example, an on-chip photodiode. A depackaging attack causes the generation of a voltage of a photodiode, and thus a change in physical state of the packaging can be detected.

A semiconductor chip may comprise: a processor for processing data; a shield which includes a metal line and is arranged over an upper portion of the processor; a detection unit for comparing a reference signal with an output signal, which is outputted when the reference signal passes through the shield, so as to detect whether there has been a wiring change within the shield or not; and a controller for configuring the routing topology of the metal line to be in a first state, and changing the routing topology from the first state to a second state.

A system-on-chip includes a processing core and a memory controller connected between the core and an external memory. A clock divider receives an internal clock signal and outputs a divided clock signal. The memory controller uses the divided clock signal to establish an interface communication frequency with the memory. A boot control logic circuit, connected to the clock divider, compares a check data pattern to a predefined data pattern read from the memory by the memory controller at the interface frequency. When the predefined and check data patterns do not match, the boot control logic circuit instructs the clock divider to adjust the divided clock signal to change the interface frequency, after which the predefined data pattern reading and comparison are repeated, and when the predefined and check data patterns match, the memory controller reads a boot program, executed by the core, from the memory at the interface frequency.

A system-on-chip includes a processing core and a memory controller connected between the core and an external memory. A clock divider receives an internal clock signal and outputs a divided clock signal. The memory controller uses the divided clock signal to establish an interface communication frequency with the memory. A boot control logic circuit, connected to the clock divider, compares a check data pattern to a predefined data pattern read from the memory by the memory controller at the interface frequency. When the predefined and check data patterns do not match, the boot control logic circuit instructs the clock divider to adjust the divided clock signal to change the interface frequency, after which the predefined data pattern reading and comparison are repeated, and when the predefined and check data patterns match, the memory controller reads a boot program, executed by the core, from the memory at the interface frequency.

Subject matter disclosed herein may relate to buffers, and may relate more particularly to non-volatile buffers for memory operations.