Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

Embodiments of the present invention may provide an improved distributed computing system. Entities in the distributed computing system may be divided into four categories: writers, readers, gateways, and applications. End users may interact with the system via the applications through the gateways. The role of writers and readers may be separated to distribute computational burdens. Writers may generate messages for an event stream. The messages may include a timestamp for consistent global ordering. The readers may arrange messages from various writers based on the timestamps to generate globally time-consistent event streams.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

The present disclosure proposes a speech chip and an electronic device. The speech chip includes: a peripheral interface connected to a speech receiver and configured to receive a speech signal; a bus matrix connected to the peripheral interface; a first processor connected to the bus matrix and configured to determine whether is the speech signal contains a wake-up word according to the speech signal; a second processor connected to the bus matrix and configured to perform signal denoising and speech recognition on the speech signal; and a memory array connected to the bus matrix.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Embodiments of the present invention may provide an improved distributed computing system. Entities in the distributed computing system may be divided into four categories: writers, readers, gateways, and applications. End users may interact with the system via the applications through the gateways. The role of writers and readers may be separated to distribute computational burdens. Writers may generate messages for an event stream. The messages may include a timestamp for consistent global ordering. The readers may arrange messages from various writers based on the timestamps to generate globally time-consistent event streams.

Embodiments of the present invention may provide an improved distributed computing system. Entities in the distributed computing system may be divided into four categories: writers, readers, gateways, and applications. End users may interact with the system via the applications through the gateways. The role of writers and readers may be separated to distribute computational burdens. Writers may generate messages for an event stream. The messages may include a timestamp for consistent global ordering. The readers may arrange messages from various writers based on the timestamps to generate globally time-consistent event streams.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.