A modular quantum computer architecture is developed with a hierarchy of interactions that can scale to very large numbers of qubits. Local entangling quantum gates between qubit memories within a single modular register are accomplished using natural interactions between the qubits, and entanglement between separate modular registers is completed via a probabilistic photonic interface between qubits in different registers, even over large distances. This architecture is suitable for the implementation of complex quantum circuits utilizing the flexible connectivity provided by a reconfigurable photonic interconnect network. The subject architecture is made fault-tolerant which is a prerequisite for scalability. An optimal quantum control of multimode couplings between qubits is accomplished via individual addressing the qubits with segmented optical pulses to suppress crosstalk in each register, thus enabling high-fidelity gates that can be scaled to larger qubit registers for quantum computation and simulation.

An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

A data processing apparatus is configured to solve a specific problem using a simple hardware. The data processing apparatus comprises a state data processing unit configured to iterate update of state data by a predetermined time evolutional process, a cost evaluation unit configured to evaluate a cost function for current state data, and an error calculation unit configured to calculate error values relating to amplitude homogeneity of the current state data, wherein the state data processing unit performs the time evolutional process on the state data to update the current state data based on the cost function and the error values which are calculated by the error calculation unit.

An acceleration system includes a plurality of modules. Each of the plurality of modules includes at least one central processing unit, at least one graphics processing unit, at least one field programmable gate array, or at least one application specific integrated circuit. At least one of the plurality of modules includes at least another of the plurality of modules such that the acceleration system is structural and nested.

A modular quantum computer architecture is developed with a hierarchy of interactions that can scale to very large numbers of qubits. Local entangling quantum gates between qubit memories within a single modular register are accomplished using natural interactions between the qubits, and entanglement between separate modular registers is completed via a probabilistic photonic interface between qubits in different registers, even over large distances. This architecture is suitable for the implementation of complex quantum circuits utilizing the flexible connectivity provided by a reconfigurable photonic interconnect network. The subject architecture is made fault-tolerant which is a prerequisite for scalability. An optimal quantum control of multimode couplings between qubits is accomplished via individual addressing the qubits with segmented optical pulses to suppress crosstalk in each register, thus enabling high-fidelity gates that can be scaled to larger qubit registers for quantum computation and simulation.

Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep learning processor then tracking one or more parameters of a deep learning program executed using the deep learning processor in the first configuration. The deep learning processor then reconfigures the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.

Novel methods of virtualization with unique virtual architectures on field-programmable gate arrays (FPGAs) are provided. A hardware security method can include providing one or more field-programmable gate arrays (FPGAs), and creating an application specialized virtual architecture (or overlay) over the one or more FPGAs (for example, by providing an overlay generator). Unique bitfiles that configure the overlays implemented on the FPGAs can be provided for each deployed FPGA. The application specialized virtual architecture can be constructed using application code, or functions from a domain, to create an overlay represented by one or more hardware description languages (e.g., VHDL).

A reconfigurable computing appliance includes a number of computing tiles. Each computing tile includes a reconfigurable processing element and a network fabric interface device configured to communicate over a network fabric. The reconfigurable processing element operates on data received from an I/O input interface and/or data received via the network fabric interface device.

A reservoir designing method executed by a computer configured to control a neural network including a reservoir and an output layer, the reservoir including a plurality of nodes and having a coupling structure randomly determined between the plurality of nodes, the output layer having a weight set on each node of the plurality of nodes. In an example, the method includes: changing the coupling structure between the plurality of nodes included in the reservoir; computing an output for an input to the neural network; updating the weight of the output layer based on the output for each of the coupling structures changed by the changing; evaluating the output according to a predetermined criterion; and selecting a predetermined coupling structure from the coupling structures changed by the changing based on an evaluation result obtained by the evaluating.

A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.