A method includes forming, over a substrate, a plurality of well taps arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of well taps is arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of well taps includes at least one first well tap. The forming the plurality of well taps comprises forming the first well tap by forming a first well region of a first type. The first well region comprises two first end areas and a first middle area arranged consecutively between the two first end areas in the second direction. The forming the first well tap further comprises implanting, in the first middle area, a first dopant of a first type, and implanting, in the first end areas, a second dopant of a second type different from the first type.

A method of manufacture for creating an NDE test specimen with predictably located one or more flaws according to a digital flaw map and of a material having an angle of refraction matching industrial workpieces for testing and training is disclosed. Comprising selecting a workpiece material for the NDE test specimen having a substantially similar angle of refraction to industrial workpieces, fabricating the NDE test specimen from the workpiece material, executing a CAD software on one or more processors of a controller computer, reading the digital flaw map comprising coordinates of the one or more flaws to be applied to the NDE test specimen, controlling a high energy beam CNC to apply the digital flaw map to the NDE test specimen, selecting the workpiece material among crystal, borosilicate glass, and acrylic, applying a laser beam at a plurality of energy points within the NDE test specimen.

A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs. as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.

Various embodiments include modeling a component fault tree for a circuit with an input-side and an output-side component. These include using a fault tree corresponding to a hazard for each respective component, obtaining information about the components of the circuit and a connection between components, and connecting the respective fault trees based on the circuit description. Each fault tree includes an input fault mode or a basic event and an output fault mode. The output fault mode and the input fault mode are each assigned to a component terminal. An output fault mode of the input-side component tree is connected to an input fault mode of the output-side component tree if: there is a connection between the assigned terminal of the input-side component and the output-side component and the output fault mode of the input-side component correlates to an input fault mode of the output-side component.

Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers.

An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type.

A method for determining fault types in a circuit design includes obtaining circuit elements, a first observation point of a first circuit element, and a first diagnostic point of a first safety circuit device. The method further includes determining a first cone of influence including a first subset of the circuit elements based on the first observation point. The first subset of the circuit elements includes the first circuit element. Further, the method includes determining a first safety cone including a second subset of the circuit elements based on the first diagnostic point. The first safety cone includes the first safety circuit device. The method further includes determining a fault type associated with the circuit elements based on an intersection between the first cone of influence and the first safety cone.

A computer-aided design system provides tolerance analysis of model assemblies. Constraints are applied to a model assembly based on user-selected surfaces. Overlay surfaces are defined at the assembly, where each of the overlay surfaces corresponds to a user-selected surface. One or more stacks are defined based on a user input, where the stacks are a measurement dimension encompassing two or more parts of the assembly. The system simulates 1) variation of the overlay surfaces across a range of variation values within a respective tolerance zone based on the tolerance specifications, and 2) alteration of the stack as a result of the variation. Based on the variation of the overlay surfaces, the system identifies a subset of the user-selected surfaces that, when varied within the respective tolerance zone, alter the stack. A database is configured to indicate 1) the user-selected surfaces and 2) respective contributor values indicating a relative contribution of each of the user-selected surfaces to the stack.

A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

A method for selecting components in a radiation tolerant electronic system, comprising, determining ionizing radiation responses of COTS devices under various radiation conditions, selecting a subset of the COTS devices whose radiation responses satisfy threshold radiation levels, applying mathematical models of the COTS devices for post-irradiation conditions to determine radiation responses to ionizing radiation; implementing a radiation-tolerant architecture using COTS devices from the selected subset, the implemented circuit may be tested for robustness to ionizing radiation effects without repeated destructive tests of the hardware circuit by using the mathematical models for simulating response to the ionizing radiation, and implementing a multi-layer shielding to protect the implemented circuit under various radiation conditions.