Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.

To support realization of efficient data conversion processing even between data with undefined conversion definition and the like. A data integration apparatus includes an arithmetic unit that calculates a similarity between a data format of a table regarding predetermined data, data format information of which has not stored in a storage device, and a master data format of each predetermined table, specifies a predetermined table in the master data format having the similarity that satisfies a predetermined criterion, calculates a similarity between the master data format of the specified predetermined table and a data format of each table of each system, specifies a predetermined table of a predetermined system having the similarity that satisfies a predetermined criterion, and outputs conversion processing definition information on the specified predetermined table in the master data format and the specified predetermined table of the predetermined system as reusable conversion processing component candidate information.

An embodiment of the present invention is directed to financial transaction ecosystems. A transaction processing ecosystem comprises: a plurality of data sources; a capture interface; and a financial transaction processing system comprising a message bus and a plurality of processors interfacing with the message bus and configured to perform: receiving, via the capture interface, raw data for a payment transaction, wherein the raw data comprises client instructions; normalizing, via the capture interface, the raw data into a normalized transaction format based on a standard data model; publishing, via the capture interface, the normalized transaction format to a message bus; processing, via a first processor of the plurality of processors, the normalized transaction format; and completing the transaction.

Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.

Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.

An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.

An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.

Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.

An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.

An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.