G06F2211/109

Failure Abatement Approach For A Failed Storage Unit
20210342224 · 2021-11-04 · ·

A method for execution by a vault management device of a storage network includes determining a failure impact level to vaults of the storage network based on a failed storage unit within the vaults, where the vaults include a first vault that is associated with a first set of storage units and a first decode threshold number, and a second vault that is associated with a second set of storage units and a second decode threshold number, and where the failure impact level is based on the number of non-failed storage units within each of the vaults. The method continues with determining a failure abatement approach based on the failure impact level. The method continues by with facilitating the failure abatement approach.

ACCELERATED ERASURE CODING SYSTEM AND METHOD
20230336191 · 2023-10-19 ·

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Composite data recovery procedure

A method of recovering data from one or more failed data sectors includes estimating a reader offset position from a first or a second read attempt of the one or more failed data sectors at a current set of channel parameters and basing the estimated reader offset position on, at least in part, a position error signal generated during the first or second read attempt. At least one read is performed on the one or more failed data sectors at the estimated reader offset position to obtain one or more samples. The one or more samples are processed to obtain a processed sample. Iterative outer code recovery is performed on the processed sample.

Resiliency scheme to enhance storage performance
11416338 · 2022-08-16 · ·

A storage system has a resiliency scheme to enhance storage system performance. The storage system composes a RAID stripe. The storage system mixes an ordering of portions of the RAID stripe, based on reliability differences across portions of the solid-state memory. The storage system writes the mixed ordering RAID stripe across the solid-state memory.

RESILIENCY SCHEME TO ENHANCE STORAGE PERFORMANCE
20210334157 · 2021-10-28 ·

A storage system has a resiliency scheme to enhance storage system performance. The storage system composes a RAID stripe. The storage system mixes an ordering of portions of the RAID stripe, based on reliability differences across portions of the solid-state memory. The storage system writes the mixed ordering RAID stripe across the solid-state memory.

Systems and methods for adaptive error-correction coding

A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising a plurality of columns. The ECC codewords may comprise ECC codeword symbols. The ECC symbols of a data segment may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The individual ECC symbols may be stored within respective columns of the array (e.g., may not cross column boundaries). Data of an unavailable ECC symbol may be reconstructed by use of other ECC symbols stored on other columns of the array.

Failure abatement approach for failed storage units common to multiple vaults
11093327 · 2021-08-17 · ·

A method includes detecting, by a vault management device, a failed storage unit common to a first vault and a second vault. The first vault is associated with a first set of storage units and the second vault is associated with a second set of storage units. The failed storage unit is in each of the first and second sets of storage units. The method further includes identifying a number of non-failed storage units of the first and second sets of storage units and comparing the number of non-failed storage units with first and second decode threshold numbers to determine a failure impact level. The first decode threshold number is associated with the first vault and the second decode threshold number is associated with the second vault. The method further includes determining a failure abatement approach based on the failure impact level and facilitating the failure abatement approach.

Systems and methods for adaptive data storage

A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising two or more solid-state storage elements. The data segments may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The data arrangement may determine input/output performance characteristics. An optimal adaptive data storage configuration may be based on read and/or write patterns of storage clients, read time, stream time, and so on. Data of failed storage elements may be reconstructed by use of parity data and/or other ECC codewords stored within the array.

Memory built-in self test error correcting code (MBIST ECC) for low voltage memories

The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

MEMORY BUILT-IN SELF TEST ERROR CORRECTING CODE (MBIST ECC) FOR LOW VOLTAGE MEMORIES

The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.