A transmitting apparatus includes a signal generation circuit and an adjustment circuit. The signal generation circuit is configured to send, to a receiving apparatus, a serial data signal that carries a training sequence and valid data, where the training sequence is used to train a skew or an equalization of the serial data signal, and the valid data is used to detect an amplitude of the serial data signal. The adjustment circuit is configured to receive indication information from the receiving apparatus, and adjust a transmission parameter of the serial data signal based on the indication information, where the transmission parameter includes at least one of the skew, the equalization, or the amplitude.

A serial connector adapter system includes a serial connector adapter device connected to a computing device. The serial connector adapter device includes a serial communication request subsystem coupled to a serial connector and a first USB connector. The computing device includes a second USB connector connected to the first USB connector, a serial communication subsystem coupled to the second USB connector, and a serial communication configuration subsystem coupled to the second USB connector and the serial communication subsystem. The serial communication configuration uses a USB ground drain connection in the first and second USB connectors subsystems to identify the serial connector adapter device and perform bi-directional communications to receive a request for serial communications with the serial communication subsystem and, in response, configures the serial communication subsystem to perform serial communications via the serial connector using USB transmitter/receiver pair connections in the first and second USB connectors.

A decoding method and a storage controller for a rewritable non-volatile memory module are provided. The method includes choosing a target word line among a plurality of word lines, wherein a plurality of target memory cells of the target word-line are programmed; reading the target memory cells by respectively using different X read voltage sets, so as to obtain X Gray code count deviation summations, wherein the X read voltage sets and the corresponding X Gray code count deviation summations are all ordered based on a first predefined order; and choosing one of the X read voltage sets as an optimized read voltage set according to the X Gray code count deviation summations.

A measuring system for measuring signals with multiple measurement probes comprises a multi probe measurement device comprising at least two probe interfaces that each couple the multi probe measurement device with at least one of the measurement probes, a data interface that couples the multi probe measurement device to a measurement data receiver, and a processing unit coupled to the at least two probe interfaces that records measurement values via the at least two probe interfaces from the measurement probes, wherein the processing unit is further coupled to the data interface and provides the recorded measurement values to the measurement data receiver, and a measurement data receiver comprising a data interface, wherein the data interface of the measurement data receiver is coupled to the data interface of the multi probe measurement device.

A decoding method and a storage controller for a rewritable non-volatile memory module are provided. The method includes choosing a target word line among a plurality of word lines, wherein a plurality of target memory cells of the target word-line are programmed; reading the target memory cells by respectively using different X read voltage sets, so as to obtain X Gray code count deviation summations, wherein the X read voltage sets and the corresponding X Gray code count deviation summations are all ordered based on a first predefined order; and choosing one of the X read voltage sets as an optimized read voltage set according to the X Gray code count deviation summations.

Embodiments are generally directed to phase lock loop bypass for board level testing of systems. An embodiment of system includes a power management block for the system; multiple IO (input/output) blocks; a phase lock loop (PLL) block for each of the IO blocks, each of the phase lock loop blocks being switchable between providing an output of a PLL clock signal or providing a replacement clock signal as clocking for the respective IO block; and a read only memory for storage of firmware. In some embodiments, the firmware includes elements to enable operation of the plurality of IO blocks utilizing replacement clocking.

A measuring system for measuring signals with multiple measurement probes comprises a multi probe measurement device comprising at least two probe interfaces that each couple the multi probe measurement device with at least one of the measurement probes, a data interface that couples the multi probe measurement device to a measurement data receiver, and a processing unit coupled to the at least two probe interfaces that records measurement values via the at least two probe interfaces from the measurement probes, wherein the processing unit is further coupled to the data interface and provides the recorded measurement values to the measurement data receiver, and a measurement data receiver comprising a data interface, wherein the data interface of the measurement data receiver is coupled to the data interface of the multi probe measurement device.

A measuring system for measuring signals with multiple measurement probes comprises a multi probe measurement device comprising at least two probe interfaces that each couple the multi probe measurement device with at least one of the measurement probes, a data interface that couples the multi probe measurement device to a measurement data receiver, and a processing unit coupled to the at least two probe interfaces that records measurement values via the at least two probe interfaces from the measurement probes, wherein the processing unit is further coupled to the data interface and provides the recorded measurement values to the measurement data receiver, and a measurement data receiver comprising a data interface, wherein the data interface of the measurement data receiver is coupled to the data interface of the multi probe measurement device.

Embodiments are generally directed to phase lock loop bypass for board level testing of systems. An embodiment of system includes a power management block for the system; multiple IO (input/output) blocks; a phase lock loop (PLL) block for each of the IO blocks, each of the phase lock loop blocks being switchable between providing an output of a PLL clock signal or providing a replacement clock signal as clocking for the respective IO block; and a read only memory for storage of firmware. In some embodiments, the firmware includes elements to enable operation of the plurality of IO blocks utilizing replacement clocking.

Methods and apparatuses are described that facilitate data communication across a serial bus. In one configuration, a transmitter configures a plurality of devices by assigning one or more trigger registers to each device of the plurality of devices and sends to each device a trigger register assignment command indicating a trigger register assigned to a device and identifying a trigger corresponding to the device. The transmitter then addresses a packet to an assigned trigger register and generates a bit-index field in the packet. Bits in the bit-index field respectively represent triggers corresponding to devices associated with the assigned trigger register, wherein each bit indicates whether one or more corresponding devices are enabled for operation. The transmitter then sends the packet to the plurality of devices via the serial bus.