A system and method for active disturbance rejection based thermal control is configured to receive, at a first active disturbance rejection thermal control (ADRC) controller, a first temperature measurement from a first thermal zone. The ADRC controller generates a first output control signal for controlling a first cooling element, wherein the first output control signal is generated according a first estimated temperature and a first estimated disturbance calculated by a first extended state observer (ESO) of the first ADRC controller.

The disclosure relates in some aspects to managing the fetching and execution of commands stored in submission queues. For example, execution of a command may be blocked at a data storage apparatus due to an internal blocking condition (e.g., a large number of commands of a particular type are pending for execution at the data storage device). As another example, execution of a command may be blocked at a data storage apparatus due to an external blocking condition (e.g., a host device may specify that certain commands are to be executed immediately one after another). The disclosure relates in some aspects to controlling how commands are fetched and executed so that commands that cannot be executed by the data storage apparatus in the near future do not prevent other commands (that are not subject to the same blocking condition) from being executed.

Techniques are provided for operating a memory package and more specifically to increasing bandwidth of a system having stacked memory. In an example, a system can include a storage device having a first type of volatile memory and a second type of volatile memory, and a host device coupled to the storage device. The host device can issue commands to the storage device to store and retrieve information of the system. The host device can include a memory map of the storage device and latency information associated with each command of the commands. The host can sort and schedule pending commands according to the latency information and can intermix commands for the first type of volatile memory and commands for the second type of volatile memory to maintain a high utilization or efficiency of a data interface between the host device and the storage device.

An aspect of the invention relates to a method of managing jobs in a information system (SI) on which a plurality of jobs run, the information system (SI) comprising a plurality of computer nodes (NDi) and at least a first storage tier (NS1) associated with a first performance tier and a second storage tier (NS2) associated with a second performance tier lower than the first performance tier, each job being associated with a priority level determined from a set of parameters comprising the node or nodes (NDi) on which the job is to be executed, the method comprising a step of scheduling the jobs as a function of the priority level associated with each job; the set of parameters used for determining the priority level also comprising a first parameter relating to the storage tier to be used for the data necessary for the execution of the job in question and a second parameter relating to the position of the data necessary for the execution of the job (TAi) in question.

A memory device is provided. The memory device comprises a memory cell array configured to store data, a command decoder configured to receive a command from the exterior to generate a first memory cell control signal, a PIM (Processor In Memory) block configured to generate a second memory cell control signal including a command for performing an internal processing operation on the basis of instructions stored therein and perform an internal processing operation on the basis of the second memory cell control signal, and an operating mode multiplexer configured to output any one of the first memory cell control signal and the second memory cell control signal and provide it to the memory cell array.

Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).

Disclosed is a memory system including a plurality of memory dies configured to store data in various storage modes; and a controller coupled with the plurality of memory dies via a plurality of channels and configured to perform a correlation operation on multiple read requests among a plurality of read requests received from a host so that the plurality of memory dies output plural pieces of data corresponding to the plurality of read requests via the plurality of channels in an interleaving way, wherein the controller is configured to determine whether to perform the correlation operation based on the number of read requests, and perform the correlation operation on the multiple read requests which are related to the same storage mode and different channels.

A data processing method includes receiving a message related to performance of a storage device, the message including an indicator value regarding the performance in a first time period, and a timestamp associated with the first time period. A status record of the storage device, including the number of received indicator values in a second time period including the first time period, is determined based on the timestamp, wherein the number of the received indicator values is less than a threshold number and can be updated based on the indicator value. The performance in the second time period can be determined based on the indicator value and the received indicator values in response to determining that the updated number of the received indicator values reaches the threshold number. Thus, the performance of the storage device can be quickly and accurately determined, and the consumption of computing resources is reduced.

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may boot an operating system; after booting the operating system, determine that a solid state drive has been hot added to a Peripheral Component Interconnect Express (PCIe) port; suppress discovery of the solid state drive by the operating system; determine a policy associated with the solid state drive; determine that a current configuration associated with the solid state drive does not match a configuration associated with the policy associated with the solid state drive; determine that the configuration associated with the policy can be applied to the solid state drive; apply the configuration associated with the policy to the solid state drive without utilizing the operating system; and inform the operating system that the solid state drive has been communicatively coupled to at least one processor via a PCIe root complex.

A memory control method and a memory storage system are provided. The method includes: in a memory closing procedure, sending, by a host system, a first control command to a memory storage device which includes a volatile memory module and a rewritable non-volatile memory module; closing, by the memory storage device, the volatile memory module in response to the first control command; and in a state where the volatile memory module is closed, maintaining, by the memory storage device, the rewritable non-volatile memory module to be operated normally.