A host includes: an index tree storing an index including information for identifying a versioning key; and an index update buffer storing a write key included in data subject to a write request and the versioning key corresponding to the write key. When a preset update condition is satisfied, the host transfers the versioning key stored in the index update buffer to the index tree, and when the index update buffer requires recovery, the host designates a recovery section of memory of the storage device including data corresponding to the versioning key which has not been updated to the index tree, to be read by a plurality of threads, reads data included in the recovery section from the storage device through the plurality of threads, and inserts the read data into the index update buffer to recover the index update buffer.

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

Methods, systems, and devices for memory operations are described. A first set of commands may be received for accessing a memory device. The first set of commands may include non-consecutive logical addresses that correspond to consecutively indexed physical addresses. A determination that the non-consecutive logical addresses correspond to consecutively indexed physical addresses may be determined based on a first mapping stored in a volatile memory. A second mapping may be transferred to the volatile memory based on the determination. The second mapping may include an indication of whether information stored at a set of physical address is valid. A second set of commands including non-consecutive logical addresses may be received for accessing the memory device. Data for the second set of commands that include the non-consecutive logical addresses may be retrieved from the memory device using the second mapping.

In an NVMe-based storage system, a host is connected to an NVMe controller through a PCIe bus, and the NVMe controller is connected to a storage medium. The NVMe controller receives from the host a data packet that carries payload data and an association identifier. The association identifier associates the payload data with a write instruction. The NVMe controller obtains the write instruction according to the association identifier, and then writes the payload data into the storage medium according to the write instruction.

In one embodiment, a system may include a memory unit, a first processing unit configured to write data into a memory region of the memory unit, a second processing unit configured to read data from the memory region, a first control unit configured to control the first processing unit's access to the memory unit and, and a second control unit configured to control the second processing unit's access to the memory unit. The first control unit may be configured to obtain, from the second control unit, a first memory address associated with a data reading process of the second processing unit, receive a write request from the first processing unit, the read request having an associated second memory address, and write data into the memory region based on the write request in response to a determination that the second memory address falls outside of the guarded reading region.

A storage controller including: a host interface circuit receiving first, second, third and fourth requests corresponding to first, second, third and fourth logical addresses; a memory interface circuit communicating with first nonvolatile memories through a first channel and second nonvolatile memories through a second channel; a first flash translation layer configured to manage the first nonvolatile memories; and a second flash translation layer configured to manage the second nonvolatile memories, the first flash translation layer outputs commands corresponding to the first and fourth requests through the first channel, and the second flash translation layer outputs commands respectively corresponding to the second and third requests through the second channel, and a value of the first logical address is smaller than a value of the second logical address, and a value of the third logical address is smaller than a value of the fourth logical address.

Techniques are disclosed for content storage in a way that facilitates consistent and concurrent read/write processing of stored documents. An example methodology implementing the techniques includes segmenting the contents of a document into a plurality of content segments and storing the plurality of content segments within a data structure, the data structure including storage blocks having storage portions and buffer portions. The storage of the plurality of content segments includes storage of content segments within a storage portions of the storage blocks of the data structure. The method also includes receiving at least one change to the content and utilizing a buffer portion of at least one storage block to store the at least one change to the content.

A system and method for logging state data from a power system control device on a computer system is disclosed. The computer system includes a power system supplying power to the computer system. The power system has a power-up sequence having a plurality of stages. The power system control device is coupled to the power system. The power system control device includes a finite state machine circuit having states corresponding to the stages of the power-up sequence. The control device also has a write controller, a storage buffer, and a communication interface. The write controller writes the state of the finite state machine circuit in the storage buffer. An external controller is coupled to the communication interface and is operable to read the stored state data.

Disclosed are systems and methods by which a storage device may process and return I/O commands to a host in the order in which the host provided the commands, thereby reducing host overhead, including but not limited to the following: receiving a first I/O command and a second I/O command, the first I/O command and the second I/O command being assigned a sequence tag, issuing the first I/O command and the second I/O command to one or more storage channels based on their respective sequence tags, collecting a command completion notice of the first I/O command or the second I/O command when the first I/O command or the second I/O command has been respectively completed; and issuing a command completion notification to a host based on the sequence tag of the associated completed first I/O command or the second I/O command.