Systems and methods for designing a chip configured to perform computing processes are provided. The described techniques include obtaining information associated with the chip and determining, using a trained machine learning model and the information associated with the chip, selections of one or more circuit building blocks to be included in the chip. The chip architecture may then be generated to be used in fabrication of the chip based on the selections of the one or more circuit building blocks.

Systems and methods for designing a chip configured to perform computing processes are provided. The described techniques include obtaining information associated with the chip and determining, using a trained machine learning model and the information associated with the chip, selections of one or more circuit building blocks to be included in the chip. The chip architecture may then be generated to be used in fabrication of the chip based on the selections of the one or more circuit building blocks.

Systems and methods for digital circuit emulation with homomorphic encryption include: receiving, by a hardware design tool chain, a customization file containing a predetermined set of one or more cells; converting, by the hardware design tool chain, a first digital circuit representation in a set of hardware design language (HDL) files into a second digital circuit representation based on the predetermined set of cells in the customization file; receiving, by an encrypted circuit emulator, a set of encrypted inputs; and executing, by the encrypted circuit emulator, the second digital circuit representation using the set of encrypted inputs to generate a set of encrypted outputs.

Systems and methods for digital circuit emulation with homomorphic encryption include: receiving, by a hardware design tool chain, a customization file containing a predetermined set of one or more cells; converting, by the hardware design tool chain, a first digital circuit representation in a set of hardware design language (HDL) files into a second digital circuit representation based on the predetermined set of cells in the customization file; receiving, by an encrypted circuit emulator, a set of encrypted inputs; and executing, by the encrypted circuit emulator, the second digital circuit representation using the set of encrypted inputs to generate a set of encrypted outputs.

A computer system traces an original electronic design automation (EDA) implementation process for electronic hardware designs. The original EDA implementation process includes multiple subprocesses to convert a hardware model to a physically-realized electronic circuit. The system inputs a cryptographic key and design information that includes the hardware model, constraints, properties, implementation settings, and other directives for directing the conversion. The cryptographic key and design information are processed to generate a sequence of instructions to execute and provide traceability of each subprocess. For each subprocess, the system gathers intermediate design state and implementation settings resulting from or influencing execution of the subprocess; combines the intermediate design state and implementation settings into a data string and determines a cryptographic hash value for the data string; digitally signs the cryptographic hash value using a digital signature certificate derived from the cryptographic key to generate a signed hash; stores the signed hash and identifiers associated with data files used for determining the cryptographic hash value to an electronic ledger to generate an updated electronic ledger; authenticates the signed hash from the electronic ledger to generate an authenticated signed hash; reconstructs a hash from the data files stored in the electronic ledger to generate a reconstructed hash; compares the authenticated signed hash with the reconstructed hash, and in response to a mismatch, generates an error signal. The steps are repeated for each subsequent subprocess, and the traced EDA implementation process results are stored in memory.

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

Embodiments described herein provide systems and methods for optimizing a Gaussian representation to design photonic circuits for preparing a given target quantum state. The systems and methods internally consider and optimize quantum representations (e.g., Gaussian transformations, Gaussian and non-Gaussian states). In some embodiments, the systems and methods may produce optimal Gaussian transformations or states. In some embodiments, the systems and methods extract circuit parameters from an optimal Gaussian transformation to produce quantum circuits or designs for generating the optimal states. Embodiments described herein relate to systems and methods for optimizing a Gaussian transformation for state generation.

Embodiments described herein provide systems and methods for optimizing a Gaussian representation to design photonic circuits for preparing a given target quantum state. The systems and methods internally consider and optimize quantum representations (e.g., Gaussian transformations, Gaussian and non-Gaussian states). In some embodiments, the systems and methods may produce optimal Gaussian transformations or states. In some embodiments, the systems and methods extract circuit parameters from an optimal Gaussian transformation to produce quantum circuits or designs for generating the optimal states. Embodiments described herein relate to systems and methods for optimizing a Gaussian transformation for state generation.

A system and method are provided for simulating circuits that transmit bidirectional signals between some ports using simulators designed originally for electrical circuits and systems, that eliminate the need for different port interfaces. The system and method can be applied to simulate photonic circuits either standalone or integrated with electrical circuits and systems. In one method implemented by the system potential and flow representations, available for example in Verilog-A simulators, are used to create bidirectional signals on a single bus line to transmit optical signals. In another method implemented by the system, the system auto-configures each optical port type as left or right at runtime or during a pre-simulation initialization to allow for bidirectional signals with a single port interface.

A system and method are provided for simulating circuits that transmit bidirectional signals between some ports using simulators designed originally for electrical circuits and systems, that eliminate the need for different port interfaces. The system and method can be applied to simulate photonic circuits either standalone or integrated with electrical circuits and systems. In one method implemented by the system potential and flow representations, available for example in Verilog-A simulators, are used to create bidirectional signals on a single bus line to transmit optical signals. In another method implemented by the system, the system auto-configures each optical port type as left or right at runtime or during a pre-simulation initialization to allow for bidirectional signals with a single port interface.