Methods and systems are provided for protecting a circuit design for an integrated circuit. Logic circuits are identified in at least a portion of the circuit design for replacement. The logic circuits in the circuit design are replaced with a bitstream and configurable circuits that comprise memory circuits. A transformed circuit design is generated for the integrated circuit that comprises the configurable circuits. The configurable circuits in the transformed circuit design perform logic functions of the logic circuits when the bitstream is stored in the memory circuits in the configurable circuits.

An integrated circuit includes logic circuits, a logic analyzer circuit, and a multiplexer circuit configurable to provide a value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store the value of the signal selected by the multiplexer circuit. A method is provided for capturing signals within an integrated circuit. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting one of the first logic signal or the second logic signal as a selected signal using the multiplexer circuit, and storing a value of the selected signal in the logic analyzer circuit in the integrated circuit.

An integrated circuit includes logic circuits, a logic analyzer circuit, and a multiplexer circuit configurable to provide a value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store the value of the signal selected by the multiplexer circuit. A method is provided for capturing signals within an integrated circuit. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting one of the first logic signal or the second logic signal as a selected signal using the multiplexer circuit, and storing a value of the selected signal in the logic analyzer circuit in the integrated circuit.

A method for computer-assisted system design includes: providing a textual system description that defines a desired behavior of a vehicle; converting, using a computer, the textual system description into a linear temporal logic (LTL) formula; converting, using the computer, the LTL formula into a first automaton; providing, using the computer, a second automaton representing system dynamics of the vehicle; and generating, using the computer, a testing automaton by combining the first and the second automaton.

The present invention discloses a method for viewing simulation signals of digital products and a simulation system, the method includes: when performing FPGA simulation on digital products, reading out all external port status data of digital products in real time and recording, meanwhile reading out all internal status data of digital products once every interval time and recording; after completing the simulation, when needing a back trace to check the data of digital products in a certain clock cycle, reading out the internal status data of digital products stored at the last time point before this clock cycle and the external port status data at said time point in the recorded simulation data; and taking the read-out data as an initial status data of the FPGA, then reading out all internal status data of digital products clock by clock until running to the clock cycle that needs to be viewed.

The present invention discloses a method for viewing simulation signals of digital products and a simulation system, the method includes: when performing FPGA simulation on digital products, reading out all external port status data of digital products in real time and recording, meanwhile reading out all internal status data of digital products once every interval time and recording; after completing the simulation, when needing a back trace to check the data of digital products in a certain clock cycle, reading out the internal status data of digital products stored at the last time point before this clock cycle and the external port status data at said time point in the recorded simulation data; and taking the read-out data as an initial status data of the FPGA, then reading out all internal status data of digital products clock by clock until running to the clock cycle that needs to be viewed.

Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop are completed.

Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop are completed.

The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.