A method for improving OpenCL hardware execution efficiency described in this invention comprises the following steps: compiling a kernel implemented in OpenCL, generating Verilog code with a high-level synthesis tool; analyzing the interfaces of auto-generated Verilog code, recording signals, timing sequence, and function of the interfaces; manually modifying and optimizing the Verilog code; inserting a file replacement command in the script responsible for flow control, replacing the auto-generated code with the optimized Verilog code; rerunning OpenCL compiler and generating an ultimate FPGA configuration file. The invention makes manual optimization of the auto-generated Verilog code becomes possible, by parsing the compilation flow of OpenCL environment and analyzing the structure and interfaces of the auto-generated Verilog code. It promotes the performance of kernels, by increasing working frequency, achieving more parallelism and taking full advantages of FPGA hardware resources, and improves the execution efficiency of OpenCL on FPGA platform significantly.

A compilation system accesses a compilation operations that can be used by a compiler to compile a design under test (DUT). The compilation system can determine a sequence of the compilation operations for the compiler to perform the compilation. The compilation system can detect a failure at a first compilation operation of the sequence of operations during the compilation of the DUT, and the compilation of the DUT can be paused after the failure is detected. The compilation system can determine a second compilation operation of the accessed compilation operations based on one or more netlist parameters of the DUT's netlist. The compilation system then modifies the sequence of compilation operations based on the second compilation operation and resumes the compilation of the DUT at the second compilation operation using the modified sequence of compilation operations.

This application discloses the implementation of a self-timed IP with optional clock-less compression and decompression at the boundaries. It also discloses system and methods for application specific integrated circuits to convert RTL code and timing constraints to self-timed circuitry with optional clock-less compression and decompression at the boundaries.

Systems and methods for application specific integrated circuit design using Chronos links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

Systems and methods for application specific integrated circuit design using Chronos links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

A system design support apparatus generates new user data on the basis of derived user data including: base user data reference information that is information specifying user data to be referred to; and information on an item changed from the user data specified by the base user data reference information and on changed contents. A system design support method includes a step of selecting user data to be used, a step of generating derived user data including: base user data reference information for specifying the selected user data to be used; and information on an item changed from the user data specified by the base user data reference information and on changed contents, and a step of generating new user data on the basis of the derived user data.

A system design support apparatus generates new user data on the basis of derived user data including: base user data reference information that is information specifying user data to be referred to; and information on an item changed from the user data specified by the base user data reference information and on changed contents. A system design support method includes a step of selecting user data to be used, a step of generating derived user data including: base user data reference information for specifying the selected user data to be used; and information on an item changed from the user data specified by the base user data reference information and on changed contents, and a step of generating new user data on the basis of the derived user data.

Systems and methods for programming field programmable gate array (FPGA) devices are provided. A trained model for a deep learning process is obtained and converted to design abstraction (DA) code defining logic block circuits for programming an FPGA device. Each of these logic block circuits represents one of a plurality of modules that executes a processing step between different layers of the deep learning process.

Systems and methods for programming field programmable gate array (FPGA) devices are provided. A trained model for a deep learning process is obtained and converted to design abstraction (DA) code defining logic block circuits for programming an FPGA device. Each of these logic block circuits represents one of a plurality of modules that executes a processing step between different layers of the deep learning process.

Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.