A processor of an aspect includes packed data registers, and a decode unit to decode an instruction. The instruction may indicate a first source packed data to include at least four data elements, to indicate a second source packed data to include at least four data elements, and to indicate a destination storage location. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, is to store a result packed data in the destination storage location. The result packed data may include at least four indexes that may identify corresponding data element positions in the first and second source packed data. The indexes may be stored in positions in the result packed data that are to represent a sorted order of corresponding data elements in the first and second source packed data.

A processor of an aspect includes packed data registers, and a decode unit to decode an instruction. The instruction may indicate a first source packed data to include at least four data elements, to indicate a second source packed data to include at least four data elements, and to indicate a destination storage location. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, is to store a result packed data in the destination storage location. The result packed data may include at least four indexes that may identify corresponding data element positions in the first and second source packed data. The indexes may be stored in positions in the result packed data that are to represent a sorted order of corresponding data elements in the first and second source packed data.

A technique relates to flash-optimized data layout of a dataset for queries. Selection columns are stored in flash memory according to a selection optimized layout, where the selection optimized layout is configured to optimize predicate matching and data skipping. The selection optimized layout, for each selection column, is formed by storing a selection column dictionary filled with unique data values in a given selection column, where the unique data values are stored in sorted order in the selection column dictionary. Row position designations are stored corresponding to each row position that the unique data values are present within the given selection column, without duplicating storage of any of the unique data values that occur more than once in the given selection column.

A technique relates to flash-optimized data layout of a dataset for queries. Selection columns are stored in flash memory according to a selection optimized layout, where the selection optimized layout is configured to optimize predicate matching and data skipping. The selection optimized layout, for each selection column, is formed by storing a selection column dictionary filled with unique data values in a given selection column, where the unique data values are stored in sorted order in the selection column dictionary. Row position designations are stored corresponding to each row position that the unique data values are present within the given selection column, without duplicating storage of any of the unique data values that occur more than once in the given selection column.

A computer-implemented method for preparing training data for a speech recognition model is provided including obtaining a plurality of sentences from a corpus, dividing each phoneme in each sentence of the plurality of sentences into three hidden states, calculating, for each sentence of the plurality of sentences, a score based on a variation in duration of the three hidden states of each phoneme in the sentence, and sorting the plurality of sentences by using the calculated scores.

A computer-implemented method for preparing training data for a speech recognition model is provided including obtaining a plurality of sentences from a corpus, dividing each phoneme in each sentence of the plurality of sentences into three hidden states, calculating, for each sentence of the plurality of sentences, a score based on a variation in duration of the three hidden states of each phoneme in the sentence, and sorting the plurality of sentences by using the calculated scores.

An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

Approaches for determining scheduling assignments for the movement of people along a multi-segment path from a starting location to a destination location, are used to manage crowds, predict crowd behavior, and mitigate crowd turbulence. For example, to mitigate crowd congestion, routing solutions specifying an amount of time to spend at a destination and a departure time can be provided. Itinerary assignments, crowd data, and data associated with an event can be analyzed and weighted to determine scheduling assignments. Scheduling assignments can be validated against current crowd data and event data. Current crowd data and event data and crowd simulation can be used to predict future crowd behavior or crowd problems. Scheduling assignments can be rescheduled to mitigate crowd problems or emergencies.