Disclosed approaches eliminate involving a bus interface in polling by the host computer system and the peripheral component for events to coordinate direct memory access (DMA) transfers. The host polls main memory for DMA events communicated by the peripheral component, and the peripheral component polls local registers for DMA addresses to initiate DMA transfers. DMA transfers are initiated by the host storing main memory addresses in the local registers of the peripheral component, and DMA events generated by the peripheral component are stored in the main memory.

Aspects disclosed in the detailed description include configuring a configurable combined private and shared cache in a processor. Related processor-based systems and methods are also disclosed. A combined private and shared cache structure is configurable to select a private cache portion and a shared cache portion.

A semiconductor device capable of shortening a time required for data transfer and data organizing is provided. The solid state device includes a processor, a memory, an external interface, registers for storing data received by the external interface, a mirror register buffer, a processor, a memory, an external interface, registers, and an internal bus connected to the mirror register buffer. Registers output data to the mirror register buffer without going through the internal bus. Mirror register buffer gives the data input from the registers an address in a mirror register buffer different from the address allocated to the register, and transfers the data to the memory without passing through the internal bus.

In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

In-flight operations in an inbound data path from a source memory to a convolution hardware circuit increase computational throughput when performing convolution calculations, such as pooling and element-wise operations. Various operations may be performed in-line within an outbound data path to a target memory. Advantageously, this drastically reduces extraneous memory access and associated read-write operations, thereby, significantly reducing overall power consumption in a computing system.

A system may include a memory array for VMM and includes a matrix of devices. The devices may be configured to receive a programming signal to program a weight to store a matrix of weights. The devices may be configured to receive a digital signal representative of a vector of input bits. The devices may generate an analog output signal by individually multiplying input bits by a corresponding weight. The system may include multiple ADCs electrically coupled to a corresponding device. Each ADC may be configured to convert a corresponding analog output signal to a digital signal based on a current level of the corresponding analog output signal. The system may include registers electrically coupled to a corresponding ADC configured to shift and store an output vector of bits of a corresponding digital output signal based on an order of the vector of input bits received by the corresponding device.

According to a first aspect, execution logic is configured to perform a linear capability transfer operation which transfers a physical capability from a partition of a first software modules to a partition of a second of software module without retaining it in the partition of the first. According to a second, alternative or additional aspect, the execution logic is configured to perform a sharding operation whereby a physical capability is divided into at least two instances, which may later be combined.

In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

The present disclosure is directed to a novel system for using a distributed register to generate, manage, and store data for interest-pooled time deposit resource accounts. The invention leverages a pooled resource account approach, allowing for multiple disparate resource accounts to benefit from an enhanced interest return by pooling resource accounts. The system components of the invention contemplate the use of distributed register technology to provide a verified ledger of information related to one or more resource accounts, as well as store system data, user data, and metadata related to the movement and management of resources. By using a distributed register approach to store and verify data related to time-dependent resource account services, the invention provides an automated system and methods for enhancing the flow of sensitive verified information, reducing the need for manual review and increasing the speed at which various resource account services can be validated and executed.

Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. Execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.