Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.

The present invention particularly concerns a method for executing a program (P) intended to be interpreted by a virtual machine (M), the method comprising steps of determination (102) of a reference code instruction to be interpreted when executing the program, interpretation (112) by the virtual machine of the reference code instruction using machine code. This method also comprises read-out (106) of interpretation rights data (DR) indicating a portion (P1) of the program containing code instructions interpretable by the virtual machine and, on the basis of read-out data, checking the presence (110) of the reference code instruction in the portion (P1) of the program (P), the interpretation of the reference code instruction being implemented by the virtual machine (M) only if the reference code instruction is contained in the portion (P1) of the program (P).

An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

Synchronization points are inserted into a program code to be monitored, and are associated with different branches resulting from execution of an indirect branch instruction. The synchronization points can be accessed by the monitored program code for the purpose of identifying which branch to use during execution of the indirect branch instruction of the monitored program code.

Management of a store queue based on a restoration operation. A determination is made as to whether a restoration operation to perform a bulk restore of a set of architected registers has completed. Based on determining that the restoration operation has completed, one or more store queue entries corresponding to the restoration operation are invalidated.

Management of a store queue based on a restoration operation. A determination is made as to whether a restoration operation to perform a bulk restore of a set of architected registers has completed. Based on determining that the restoration operation has completed, one or more store queue entries corresponding to the restoration operation are invalidated.

A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.

Register restoration using transactional memory register snapshots. An indication that a transaction is to be initiated is obtained. Based on obtaining the indication, a determination is made as to whether register restoration is in active use. Based on obtaining the indication and determining register restoration is in active use, register restoration is deactivated. To recover one or more architected registers of the transaction, a transactional rollback snapshot is created.

Register restoration using transactional memory register snapshots. An indication that a transaction is to be initiated is obtained. Based on obtaining the indication, a determination is made as to whether register restoration is in active use. Based on obtaining the indication and determining register restoration is in active use, register restoration is deactivated. To recover one or more architected registers of the transaction, a transactional rollback snapshot is created.

Sharing snapshots between restoration and recovery. A snapshot to be used for recovery and restoration is obtained. The snapshot includes restoration state for a plurality of architected registers. The plurality of architected registers includes one or more architected registers associated with an instruction to alter an execution path and one or more architected registers associated with a save request. At least one architected register of the plurality of architected registers is restored, based on a request. The request is a recovery request to recover at least one architected register associated with the instruction to alter the execution path or a restoration request to restore at least one architected register associated with the save request.