A computer system having an address system of a first predetermined width in which each address of the first predetermined width in the address system includes a first portion identifying an object and a second portion identifying an offset relative to the object, where a static identifier for the first portion is predetermined to identify an address space having a second predetermined width that is smaller than the first predetermined width, or a space of kernel objects.

Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.

In one embodiment, a data mover accelerator is to receive, from a first agent having a first address space and a first process address space identifier (PASID) to identify the first address space, a first job descriptor comprising a second PASID selector to specify a second PASID to identify a second address space. In response to the first job descriptor, the data mover accelerator is to securely access the first address space and the second address space. Other embodiments are described and claimed.

A method includes receiving, from a database management system, a view instruction, using a single band descriptor able to describe 2**60 words of space, defined as a data expanse; creating, by an operating system, the data expanse in response to the view instruction; and allowing an activity to access a subset of the data expanse with a postern; wherein fast access to data whose size exceeds the available virtual address space is available. A computer program product may include a non-transitory computer-readable medium comprising instructions which, when executed by a processor of a computing system, cause the processor to perform the following actions: receiving, from a database management system, a view instruction, using a single band descriptor able to describe 2**60 words of space, defined as a data expanse; creating, by an operating system, the data expanse in response to the view instruction; and allowing an activity to access a subset of the data expanse with a postern; wherein fast access to data whose size exceeds the available virtual address space is available.

An integrated circuit includes: a processor; a memory coupled to the processor; and a stack memory allocation controller coupled to the processor and the memory. The stack memory allocation controller has: a stack use manager configured to monitor activities of the processor. The stack memory allocation controller also has a virtual memory translator configured to: obtain a first mapping of pointers to a first sub-set of memory blocks of the memory assigned to a memory stack for a thread executed by the processor; and determine a second mapping of pointers to a second sub-set of memory blocks of the memory assigned to the memory stack and different than the first sub-set of memory blocks responsive to the monitored activities.

A computer system having an address system of a first predetermined width in which each address of the first predetermined width in the address system includes a first portion identifying an object and a second portion identifying an offset relative to the object, where a static identifier for the first portion is predetermined to identify an address space having a second predetermined width that is smaller than the first predetermined width, or a space of kernel objects.

A method, an apparatus, and an electronic device for controlling memory access are disclosed. According to an embodiment, there is provided a method for controlling access to a memory including a plurality of memory modules configured in parallel. The method comprises: receiving an access instruction including an addressing field which comprise a parallel control field for controlling parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an addresses within a memory module; parsing the access instructions to determine the parallel control field, the module address field and the in-module address field; determining one or more memory modules to be accessed based on the parallel control field and the module address field; and accessing one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field.

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

A method of allocating a virtual register stack (10) of a processing unit in a stack machine is provided. The method comprises allocating a given number of topmost elements (11) of the virtual register stack (10) in a physical register file (17) of the stack machine and allocating subsequent elements of the virtual register stack (10) in a hierarchical register cache (13) of the stack machine.

Systems and methods for controlling machine operations are provided. A number of data entries are organized into a stack. Each data entry includes a type, a flag, a length, and a value or pointer entry. For each data entry in the stack, the type of data is determined from the type entry, the presence of an address or value is determined by the respective flag entry, and a length of the address or value is determined from the respective length entry. The data to be utilized or an address for the same at a particular electronic storage area is provided at the respective value or pointer entry, which may be specified by a space definition pushed onto the stack.