The present disclosure describes transaction-enabling systems and methods. A system can include a controller and a fleet of machines, each having at least one of a compute task requirement, a networking task requirement, and an energy consumption task requirement. The controller may include a resource requirement circuit to determine an amount of a resource for each of the machines to service the task requirement for each machine, a forward resource market circuit to access a forward resource market, and a resource distribution circuit to execute an aggregated transaction of the resource on the forward resource market.

The city management support apparatus is an apparatus supporting management of a city in which a plurality of services sharing a physical resource are provided. The city management support apparatus receives an input of information on a provision status of the resource, and receives an input of a service definition for each of the plurality of services. The city management support apparatus calculates a time transition of dependency of the plurality of services on the resource based on the service definition for each of the plurality of services, and detects a competition for acquisition of the resource among the plurality of services based on the time transition of the dependency. The city management support apparatus generates a proposed amendment to the service definition for at least one of the plurality of services so as to optimize the competition for the acquisition of the resource among the plurality of services.

Accelerated synchronization operations using fine grain dependency check are disclosed. A graphics multiprocessor includes a plurality of execution units and synchronization circuitry that is configured to determine availability of at least one execution unit. The synchronization circuitry to perform a fine grain dependency check of availability of dependent data or operands in shared local memory or cache when at least one execution unit is available.

A system for updating a hypercube includes an interface and a processor. The interface is configured to receive an indication to update a cell of the hypercube. The processor is configured to determine a primary dimension value associated with the cell; determine a group of dependencies based at least in part on the primary dimension value, wherein a dependency of the group of dependencies comprises one or more primary dimension values and a pattern; for the dependency of the group of dependencies, determine a set of source locations based at least in part on the one or more primary dimension values and the pattern; and mark the set of source locations as invalid.

The present disclosure provides a computation device. The computation device is configured to perform a machine learning computation, and includes an operation unit, a controller unit, and a conversion unit. The storage unit is configured to obtain input data and a computation instruction. The controller unit is configured to extract and parse the computation instruction from the storage unit to obtain one or more operation instructions, and to send the one or more operation instructions and the input data to the operation unit. The operation unit is configured to perform operations on the input data according to one or more operation instructions to obtain a computation result of the computation instruction. In the examples of the present disclosure, the input data involved in machine learning computations is represented by fixed-point data, thereby improving the processing speed and efficiency of training operations.

A processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a first load instruction included in a plurality of load instructions to generate a first decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instructions use a same register. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the first load instruction according to the first decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instructions use the same register, the data buffer is configured to store the first address generated from the address generator, and store data requested by the first load instruction according to the first address.

Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.

The present disclosure relates to a mechanism for issuing instructions in a processor (e.g., a vector processor) implemented as an overlay on programmable hardware (e.g., a field programmable gate array (FPGA) device). Implementations described herein include features for optimizing resource availability on programmable hardware units and enabling superscalar execution when coupled with a temporal single-instruction multiple data (SIMD). Systems described herein involve an issue component of a processor controller (e.g., a vector processor controller) that enables fast and efficient instruction issue while verifying that structural and data hazards between instructions have been resolved.

Techniques relating to register file prefetch are described. In an embodiment, execution circuitry causes issuance of a prefetch request to copy data from a data cache unit to a register file. Other embodiments are also disclosed and claimed.

Disclosed in some examples, are systems, methods, devices, and machine readable mediums which use improved dynamic programming algorithms to pack conditional branch instructions. Conditional code branches may be modeled as directed acyclic graphs (DAGs) which have a topological ordering. These DAGs may be used to construct a dynamic programming table to find a partial mapping of one path onto the other path using dynamic programming algorithms.