Embodiments described herein are generally directed to improving performance of a transactional API protocol by scheduling function calls based on data dependencies. In an example, a function associated with the transactional API is received that is to be carried out by an executer on behalf of an application. It is determined whether the function has a dependency on a value that is invalid. If so, execution of the function is delayed by causing a function ID of the function to be queued for a global memory reference associated with the value. After the value becomes valid, the function is caused to be executed by the executer. When the first function is determined to have no such dependency, the function may be immediately scheduled for execution by the executer without delay.

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

The present disclosure provides technical solutions related to action undo service based on cloud platform. Related operations dependent on target operations to be undone may be obtained by dependency analysis and the target operations and the related operations may be undone by time sequence so as to reduce the conflict caused by the undo operations.

A master device issues memory burst transaction requests via an interconnection bus to fetch data from a slave device. A cipher engine is coupled to the interconnection bus and decrypts the fetched data to produce plaintext data for the master device. The cipher engine selectively operates according to a stream cipher operation mode, or a block cipher operation mode. The cipher engine is configured to stall a read data channel of the interconnection bus between the slave device and the master device in response to the cipher engine switching from the block cipher operation mode to the stream cipher operation mode. The read data channel is reactivated in response to a last beat of a read burst of the plaintext data produced by the cryptographic engine.

A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.

Systems and methods are provided for management of processor thread used in support of workspaces operating on an IHS (Information Handling System), where the workspaces operate in isolation from the operating system of the IHS. A remote workspace orchestration service manages deployment of workspaces on the IHS. The workspaces are instantiated and operate according to a workspace definition provided by the workspace orchestration service. A remote access controller of the IHS determine one or more processor threads of the IHS used in support of the workspaces. The remote access controller monitors memory utilization by the processor threads used in support of the workspaces in order to detect memory thrashing resulting from the operation of a particular workspace. Based on the monitored memory utilization, the processor threads used in support of the workspaces are modified in order to reduce memory thrashing during the operation of the workspaces.

An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

A method for processing data exactly once using transactional stream writes includes receiving, from a client, a batch of data blocks for storage on memory hardware in communication with the data processing hardware. The batch of data blocks is associated with a corresponding sequence number and represents a number of rows of a table stored on the memory hardware. The method also includes partitioning the batch of data blocks into a plurality of sub-batches of data blocks. For each sub-batch of data blocks, the method further includes assigning the sub-batch of data blocks to a buffered stream; writing, using the assigned buffered stream, the sub-batch of data blocks to the memory hardware; updating a storage log with an intent to commit the sub-batch of data blocks using the assigned buffered stream; and committing the sub-batch of data blocks to the memory hardware.

The invention relates to a data processing system and a date processing method. The data processing system is configured to perform a hardware transactional memory (HTM) transaction. The data processing system comprises a byte-addressable nonvolatile memory for persistently storing data and a processor being configured to execute an atomic HTM write operation in connection with committing the HTM transaction by writing an indicator to the nonvolatile memory indicating the successful commit of the HTM transaction.