A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

The invention is notably directed at a device for high-dimensional computing comprising an associative memory module. The associative memory module comprises one or more planar crossbar arrays. The one or more planar crossbar arrays comprise a plurality of resistive memory elements. The device is configured to program profile vector elements of profile hypervectors as conductance states of the resistive memory elements and to apply query vector elements of query hypervectors as read voltages to the one or more crossbar arrays. The device is further configured to perform a distance computation between the profile hypervectors and the query hypervectors by measuring output current signals of the one or more crossbar arrays. The invention further concerns a related method and a related computer program product.

The inventive disclosures described herein pertain to an improved physical analog computer that features the ability to evaluate arbitrary non-linear functions using an interpolation method based on Chebyshev polynomials. What has been developed is an improved method for non-linear-function generation in hybrid computing that relies on Chebyshev interpolation. The method requires an initial computation of the interpolation coefficients, which is to be carried out in the digital domain. These coefficients, along with the domain of definition of the non-linear function to be generated, are used during the programming of the analog domain to set multiplier and summer elements.

The inventive disclosures described herein pertain to an improved physical analog computer that features the ability to evaluate arbitrary non-linear functions using an interpolation method based on Chebyshev polynomials. What has been developed is an improved method for non-linear-function generation in hybrid computing that relies on Chebyshev interpolation. The method requires an initial computation of the interpolation coefficients, which is to be carried out in the digital domain. These coefficients, along with the domain of definition of the non-linear function to be generated, are used during the programming of the analog domain to set multiplier and summer elements.

The inventive disclosures described herein pertain to an improved physical analog computer that features the ability to evaluate arbitrary non-linear functions using an interpolation method based on Chebyshev polynomials. What has been developed is an improved method for non-linear-function generation in hybrid computing that relies on Chebyshev interpolation. The method requires an initial computation of the interpolation coefficients, which is to be carried out in the digital domain. These coefficients, along with the domain of definition of the non-linear function to be generated, are used during the programming of the analog domain to set multiplier and summer elements.

The inventive disclosures described herein pertain to an improved physical analog computer that features the ability to evaluate arbitrary non-linear functions using an interpolation method based on Chebyshev polynomials. What has been developed is an improved method for non-linear-function generation in hybrid computing that relies on Chebyshev interpolation. The method requires an initial computation of the interpolation coefficients, which is to be carried out in the digital domain. These coefficients, along with the domain of definition of the non-linear function to be generated, are used during the programming of the analog domain to set multiplier and summer elements.

A device performs a matrix-vector multiplication of a matrix with a vector. The device includes a crossbar array having row lines, column lines and junctions arranged between the row lines and the column lines. Each junction includes a programmable resistive element and an access element for accessing the programmable resistive element. The device further includes a signal generator configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication. The device further includes a readout circuit and control circuitry configured to control the signal generator and the readout circuit. The readout circuit is configured to apply read voltages having a positive voltage sign and negative read voltages having a negative voltage sign to the row lines of the crossbar array. The readout circuit is further configured to read out column currents of the plurality of column lines of the crossbar array.

A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.

A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.