A message based processor system (1) with a plurality of message based processor system cores (100) is proposed. Cores therein comprise a processor element controller that is configured to receive a message with an indication of a subset processor elements in the core to which it is directed as well as an indication of a target pattern, and to update the state value of the processor elements (Ei) in the subset in accordance with a specification of the target pattern. The processor element controller (PEC) is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from the cyclic set dependent on a control value of a currently applied pattern element. Therewith a target pattern can efficiently specified.

A method of performing a reshape operation specified in a reshape layer of a neural network model is described. The reshape operation reshapes an input tensor with an input tensor shape to an output tensor with an output tensor shape. The tensor data that has to be reshaped is directly routed between tile memories of the hardware accelerator in an efficient manner. This advantageously optimizes usage of memory space and allows any number and type of neural network models to be run on the hardware accelerator.

Embodiments of this application disclose a data labeling system and method, and a data labeling manager. The system includes a data labeling manager, a labeling model storage repository, and a basic computing unit storage repository. The data labeling manager receives a data labeling request, obtains a target basic computing unit, allocates a hardware resource to the target basic computing unit, establishes a target computing unit, obtains first storage path information of basic parameter data of a first labeling model, and sends the first storage path information to the target computing unit. The target computing unit obtains the basic parameter data of the to-be-used labeling model by using the first storage path information, combines a target model inference framework and the basic parameter data of the first labeling model to obtain the first labeling model, and labels to-be-labeled data by using the first labeling model.

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

The present disclosure relates to circuitry for performing a multiply-accumulate (MAC) operation. The circuitry comprises a first multiplexer having a plurality of inputs for receiving a plurality of unary-coded input signals representing operands of the MAC operation and an output for outputting a multiplexer output signal representing a result of the MAC operation and a first vector quantizer configured to receive a plurality of weighting signals, each representing a proportion of a computation time period for which a respective one of the unary-coded input signals should be selected by the multiplexer and to output a first selector signal to the multiplexer to cause the multiplexer to select each of the input signals in accordance with the plurality of weighting signals.

Apparatuses, systems, and techniques to detect loops in neural network graphs. In at least one embodiment, one or more loops are detected within one or more graphs corresponding to one or more neural networks.

A method comprising: receiving an input tensor having a shape defined by [n.sub.1, ...,n.sub.k], where k is equal to a number of dimensions that characterize the input tensor; receiving tile tensor metadata comprising: a tile tensor shape defined by [t.sub.1, ..., t.sub.k], and information indicative of an interleaving stride to be applied with respect to each dimension of the tile tensor; constructing an output tensor comprising a plurality of the tile tensors, by applying a packing algorithm which maps each element of the input tensor to at least one slot location of one of the plurality of tile tensors, based on the tile tensor shape and the interleaving stride, wherein the interleaving stride results in non-contiguous mapping of the elements of the input tensor, such that each of the tile tensors includes a subset of the elements of the input tensor which are spaced within the input tensor according to the interleaving stride.

A distributed data processing system includes a processing center or algorithm persistence system (“APS”), a series of remote caching nodes in electronic communication with the APS, and a series of remote computing or processing nodes in electronic communication with the remote caching nodes. Each remote caching node is mounted to a top surface of a mobile vehicle and includes a data transmitter/receiver (transceiver), computer hardware and software to operate the caching node, memory to transmit or transfer data from the APS to the remote processing nodes. The remote processing nodes include a series of electricity generating solar panels, a series of electronic data processing chips, electronic data memory, an electronic date transmitter/receiver (transceiver), and a motion sensor. The series of electronic data processing chips are preferably a tensor processing unit (TPU), which is an AI accelerator application-specific integrated circuit (ASIC) developed specifically for neural network machine learning.

A distributed data processing system includes a processing center or algorithm persistence system (“APS”), a series of remote caching nodes in electronic communication with the APS, and a series of remote computing or processing nodes in electronic communication with the remote caching nodes. Each remote caching node is mounted to a top surface of a mobile vehicle and includes a data transmitter/receiver (transceiver), computer hardware and software to operate the caching node, memory to transmit or transfer data from the APS to the remote processing nodes. The remote processing nodes include a series of electricity generating solar panels, a series of electronic data processing chips, electronic data memory, an electronic date transmitter/receiver (transceiver), and a motion sensor. The series of electronic data processing chips are preferably a tensor processing unit (TPU), which is an AI accelerator application-specific integrated circuit (ASIC) developed specifically for neural network machine learning.

Provided is a three-dimensional vertical memory device including: a semiconductor substrate, a vertical columnar channel region provided on the semiconductor substrate and having a void of a predetermined size therein; a source electrode and a drain electrode spaced apart from each other with the channel region interposed therebetween; and a gate stack formed on the channel region.