A display driving module, a display driving method, and a display device are provided. The display driving module includes a clock signal line, a clock signal generating circuit and a gate driving circuit, where the gate driving circuit includes multiple stages of gate driving units; the clock signal generating circuit is electrically connected to the clock signal line and is configured to generate at least two clock signals and provide different clock signals to the clock signal line in a time-sharing manner; the gate driving unit is electrically connected to the clock signal line and configured to generate a gate driving signal according to the clock signals on the clock signal line; when potentials of the clock signals are valid voltages, the potentials of different clock signals are different.

A method provided by the present application comprises: obtaining a number n of rows of pixel units to be precharged; controlling a scanning driving chip to sequentially output n first scanning enable signals to a scanning driving circuit according to the number n of rows; and outputting a second scanning enable signal to the scanning driving circuit, so that the scanning driving circuit is controlled to output a second scanning signal to the pixel units of the n-th row to charge the pixel units of the n-th row.

Provided is a display device including a driving transistor, a switching unit, and a control unit. The driving transistor includes a control terminal, a first terminal, and a second terminal, and controls supply of current to a light emitting element, which is connected to the first terminal and emits light in accordance with the current amount, in accordance with a signal voltage applied to the control terminal. The switching unit can switch a conduction and non-conduction state, and, by being brought in the conduction state, forms a path that bypasses the light emitting element so that the current is not supplied to the light emitting element. The control unit performs control so that the switching unit is brought in the non-conduction state after the signal voltage is written into the control terminal, and controls a potential of the control terminal in synchronization with the control of the switching unit.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for displaying an image on a flat panel display with an array of pixels. A method includes receiving image data including a grayscale value for each pixel; determining a grayscale delta for each pixel where the grayscale delta is a variation between the grayscale value for a given pixel addressable by a first scan line and the grayscale value for another pixel addressable by a scan line addressed prior to the first scan line; determining an aggregated grayscale delta for the first scan line; comparing a magnitude of the aggregated grayscale delta to a threshold value corresponding to a data signal that results in line crosstalk; modifying the image data when the magnitude of the aggregated grayscale delta equals or exceeds the threshold value, and displaying the image on the flat panel display using the modified image data.

The present disclosure provides an electrostatic protection circuit and a display panel, wherein the electrostatic protection circuit includes a first voltage reference unit configured to divide a voltage between an array substrate row driving signal line and a common electrode line once; a second voltage reference unit configured to divide the voltage between the array substrate row driving signal line and the common electrode line twice; and a charge releasing unit that adjusts charge distribution between the array substrate row driving signal line and the common electrode line based on reference voltages provided by the first voltage reference unit and the second voltage reference unit.

A clock and voltage generation circuit includes a voltage generator which generates a first gate high voltage, a first gate low voltage, a second gate high voltage, and a second gate low voltage, a first level shifter which generates a first gate clock signal which swings between the first gate high voltage and the first gate low voltage in synchronization with a gate pulse signal, and a second level shifter which generates a second gate clock signal which swings between the second gate high voltage and the second gate low voltage in synchronization with the gate pulse signal. The voltage generator lowers the second gate high voltage to a voltage level of a kickback reference voltage in response to a kickback signal, and the first gate low voltage and the second gate high voltage are gate-on voltages, and the first gate high voltage and the second gate low voltage are gate-off voltages.

A method for driving an electro-optic display, the display having at least one display pixel coupled to a storage capacitor, the method include applying a waveform sequence to the at least one display pixel and connecting the storage capacitor to a first bias voltage, and maintaining a last frame voltage level on the display pixel after the completion of the applied waveform.

A display device includes: a display unit including a first display area, and a second display area; a scan driver configured to provide a scan signal to each scan line connected to the plurality of first pixels and the plurality of second pixels; and an emission controller configured to provide an emission control signal to each emission control line connected to the plurality of first pixels and the plurality of second pixels, wherein the plurality of first pixels have a first density in the first display area, the plurality of second pixels have a second density less than the first density in the second display area, and the plurality of second pixels include at least one sub pixel including one boosting capacitor.

An electro-optic display having at least one row of display pixels, the display include a first display pixel of the at least one row of display pixels, the first display pixel coupled to a first bias line, and a second display pixel of the at least one row of display pixels, the second display pixel coupled to a second bias line, wherein the second bias line is different from the first bias line.

A driving chip includes a data channel block including a plurality of data channels, a scan channel block disposed in a first direction from the data channel block and including a plurality of scan channels, a data pad block disposed outside the data channel block and the scan channel block in the first direction and including a plurality of data pads which respectively receive a data signal from the plurality of data channels, and a scan pad block disposed outside the data channel block and the scan channel block in the first direction, disposed outside the data pad block in a second direction crossing the first direction and including a plurality of scan pads which respectively receive a scan signal from the scan channels.