The embodiments of the application disclose a control device for a gate driving circuit, a display panel and a display device. The control device for a gate driving circuit provided in the embodiment comprises a level shifter and a control module electrically connected with an output of the level shifter. The control module is used for controlling an output signal of the level shifter to be a low level signal when each input clock signal for the level shifter is low.

A self-compensating circuit for controlling pixels in a display includes a plurality of light-emitter circuits. Each light-emitter circuit includes a light emitter, a drive transistor, and a compensation circuit. The compensation circuit is connected to the light emitter of one or more different light-emitter circuits.

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

In a matrix device having two or more systems of electrode groups such as X and Y systems, the one or more electrode groups are grouped into groups each consisting of a plurality of pixel electrodes, connection wires are branched off and connected to the pixel electrodes so that the same signal is not supplied to the pixel electrodes of the same group but the same signal is supplied to one pixel electrode of two or more groups, switching elements are provided corresponding to the individual pixel electrodes, and a gate electrode and a gate insulating film of the switching elements are used in common in the same group. Accordingly, in the matrix device and manufacturing of the matrix device, the number of connection wires and driver ICs is reduced.

A display device includes a display area including a plurality of pixels and a plurality of scan lines connected to the plurality of pixels, and a driving circuit portion that generates a compensation data voltage to compensate for a difference in length between the plurality of scan lines to input the compensation data voltage to a pixel disposed in a first area, based on start scan line information indicating a start of the first area including scan lines of the plurality of scan lines, and end scan line information indicating an end of the first area.

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

A gate driving circuit includes a plurality of unit stages connected to each other, wherein each of the plurality of unit stages includes a first transistor having a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer, a first capacitor defined by a first region in which the lower gate electrode and the upper gate electrode overlap, and a second capacitor defined by a second region in which the upper gate electrode and the first electrode overlap, wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor.

A shift register, a gate drive circuit, and a display panel are provided. The shift register includes an input sub-circuit configured to pre-charge a pull-up node using an input signal; an output sub-circuit configured to output a clock signal through an signal output terminal; a pull-down control sub-circuit configured to control a potential of a pull-down node using a power supply voltage signal; a first pull-down sub-circuit configured to pull down a potential of the pull-down node using a first preset voltage signal; and a first control sub-circuit configured to control the potential of the pull-up node using a second preset voltage signal in response to the potential of the pull-down node; a potential of the first preset voltage signal is lower than a potential of a non-operating level signal of the first pull-down sub-circuit, but higher than a potential of the second preset voltage signal.

A method of displaying an image in a display device may include determining the degree of deterioration of pixels included in a display unit based on image data of a current frame image, determining a shift route of the current frame image so as to correspond to the determined degree of deterioration. The first image data is corrected to second image data so that the current frame image is shifted along the shift route.

A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit provided on one plane. The driver circuit includes a selection circuit and a buffer circuit. The buffer circuit includes a first transistor and a second transistor. Sources of the first and second transistors are electrically connected with each other. Drains of the first and second transistors are electrically connected with each other. Gates of the first and second transistors are electrically connected with each other. The first transistor and the second transistor are stacked so that the direction of the current flow in the first transistor is parallel to that in the second transistor.