Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.

Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.

Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.