Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line, a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.

A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.

A memory device includes a memory cell array including a select transistor and a plurality of memory cells connected in series, each memory cell including a cell transistor and a variable resistance layer connected in parallel. During a write operation, a voltage setting circuit is controlled to apply a first voltage to a selected word line and a second voltage to non-selected word lines. The time period for applying the first voltage to the selected word line starts later than the time period for applying the second voltage to the non-selected word lines and ends earlier than the time period for applying the second voltage to the non-selected word lines.

Disclosed is a memory device including a magnetic storage element. The memory device includes a memory cell array, a voltage generator, and a write driver. The memory cell array includes a first region and a second region. The memory device is configured to store a value of a first read current determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of a programmed memory cell. The sensing circuit is configured to generate the first read current based on the value of the first read current and to perform a read operation on the first region based on the first read current.

A memory device includes a plurality of resistive random access memory (RRAM) cells commonly connected between a bit line (BL) and a source line (SL). Each of the RRAM cells includes a resistor, a first transistor, and a second transistor coupled to each other in series, with the resistor connected to the BL and the second transistor connected to the SL. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage, the first threshold voltage being less than the second threshold voltage.

Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Technologies relating to crossbar array circuits with parallel ground lines are disclosed. An example crossbar array circuit may include a plurality of transistors. The crossbar array circuit may include an RRAM device connected in series with a first transistor and a second transistor; a first bit line connected to the RRAM device; and a grounding line connected to a body terminal of the first transistor. The grounding line is parallel to the first bit line. In some embodiments, the first transistor is an NMOS transistor. The second transistor is a PMOS transistor

A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.

An example ternary content addressable memory. A bit cell of the memory may include first and second memristors, with a first terminal of the first memristor being connected to a first terminal of the second memristor via a node, a second terminal of the first memristor being switchably connected to a first data line, and a second terminal of the second memristor being switchably connected to a second data line. The bit cell may also include a match-line transistor that is connected between a first rail and a match line, with a gate of the match-line transistor being connected to the node.