A memory device may include: a memory bank comprising a first cell mat used as a normal area and a second cell mat used as a row hammer area and a redundancy area; a target address generation circuit suitable for: saving, in the row hammer area, a count of a received address for an active operation on the memory bank by performing an internal access operation on the row hammer area during the active operation, and setting, a particular count which satisfies a preset condition, an address corresponding to the particular count as a target address; a refresh control circuit suitable for controlling a smart refresh operation on the target address; and a column repair circuit suitable for repairing, when a bit line of the normal area has a defect, the bit line of the normal area with a bit line of the redundancy area.

Exemplary methods, apparatuses, and systems include determining that data in a group of memory cells of a first memory device is to be moved to a spare group of memory cells. The group of memory cells spans a first dimension and a second dimension that is orthogonal to the first dimension and the spare group of memory cells also spans the first dimension and the second dimension. The data is read from the group of memory cells along the first dimension of the group of memory cells. The data is written to the spare group of memory cells along the second dimension of the spare group of memory cells.

According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Embodiments provide a method and an apparatus for repairing a fail location. When repairing a fail location of a wafer, a fail bit in a wafer to be processed may be first determined, and a target potential fail bit associated with the fail bit may be determined based on a potential mining rule included in a mining rule library.

Memory device data-access schemes are disclosed. Various embodiments may include a memory device including a first column plane, a second column plane, and a data-steering circuit. The first column plane may include a first edge, a second edge, and a first number of digit lines arranged between the first edge and the second edge. The second column plane may include a third edge positioned adjacent to the second edge, a fourth edge, and a second number of digit lines arranged between the third edge and the fourth edge. The data-steering circuit may be configured to logically relate a first digit line of the first number of digit lines to a second digit line of the second number of digit lines, the first digit line proximate to the first edge and the second digit line proximate to the fourth edge. Associated systems and methods are also disclosed.

Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.

A memory system is provided. The memory system includes a compare circuit and a control circuit. The compare circuit determines, in response to a number of detected error bits in a read data from a first memory array, whether a fail word address associated with the detected error bits is in an error table. The control circuit increments a counter value corresponding to the fail word address when the fail word address is in the error table, and further compares the counter value with a threshold value to replace memory locations, corresponding to the fail word address, in the first memory array with backup memory locations in a second memory array.

Memory device data-access schemes are disclosed. Various embodiments may include a memory device including a first column plane, a second column plane, and a data-steering circuit. The first column plane may include a first edge, a second edge, and a first number of digit lines arranged between the first edge and the second edge. The second column plane may include a third edge positioned adjacent to the second edge, a fourth edge, and a second number of digit lines arranged between the third edge and the fourth edge. The data-steering circuit may be configured to logically relate a first digit line of the first number of digit lines to a second digit line of the second number of digit lines, the first digit line proximate to the first edge and the second digit line proximate to the fourth edge. Associated systems and methods are also disclosed.

Methods, apparatus, systems and articles of manufacture to facilitate an atomic operation and/or a histogram operation in cache pipeline are disclosed. An example system includes a cache storage coupled to an arithmetic component; and a cache controller coupled to the cache storage, wherein the cache controller is operable to: receive a memory operation that specifies a set of data; retrieve the set of data from the cache storage; utilize the arithmetic component to determine a set of counts of respective values in the set of data; generate a vector representing the set of counts; and provide the vector.

Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.