A semiconductor apparatus may include: a command generation circuit configured to generate a first internal command signal and a second internal command signal, which are sequentially activated on the basis of a data command signal for a data driving operation; an impedance setting circuit enabled on the basis of the first internal command signal, and configured to set impedance into which a reference resistance is reflected; and a data driving circuit enabled on the basis of the second internal command signal, and configured to perform the data driving operation on the basis of the set impedance.

A method for testing a memory chip includes the following: test data is written into memory cells of a memory chip to be tested; stored data is read from memory cells; a test result of the memory chip to be tested is generated according to the test data and the stored data. A current voltage of bit line precharge (VBLP) of the memory chip to be tested is smaller than a standard VBLP of the memory chip to be tested, and/or a current sensing delay time (SDT) of the memory chip to be tested is smaller than a standard SDT of the memory chip to be tested.

A method can include, in an integrated circuit device: at a unidirectional command-address (CA) bus having no more than four parallel inputs, receiving a sequence of no less than three command value portions; latching each command value portion in synchronism with rising edges of a timing clock; determining an input command from the sequence of no less than three command value portions; executing the input command in the integrated circuit device; and on a bi-directional data bus having no more than six data input/outputs (IOs), outputting and inputting sequences of data values in synchronism with rising and falling edges of the timing clock. Corresponding devices and systems are also disclosed.

A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

A memory circuit includes a pre-charging circuit and a control circuit. The pre-charging circuit includes a first pre-charging unit, a second pre-charging unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal; the first pre-charging unit is connected with the first power supply terminal, the first control terminal and the data terminal; the second pre-charging unit is connected with the second power supply terminal, the second control terminal and the data terminal. The control circuit is configured to in response to a memory being in a row active state and not performing a reading-writing operation, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected.

An impedance calibration circuit, an impedance calibration method, and a memory are provided. The impedance calibration circuit includes a parameter module, an initial value generation module, and a calibration module. The parameter module is configured to perform environment detection processing and output an environment parameter signal; the initial value generation module is configured to receive the environment parameter signal, and output an initial calibration value based on the environment parameter signal when the calibration instruction signal is received; and the calibration module is configured to receive the initial calibration value, and perform impedance calibration processing based on the initial calibration value when the calibration instruction signal is received.

A semiconductor structure and a memory are provided. The semiconductor structure includes a first active area; a first gate located on the first active area, the first active area and the first gate being configured to form a first transistor; a second active area, the second active area and the first active area being arranged along a first direction, the second active area and the first active area being independent from each other; a second gate located on the second active area, and the second active area and the second gate being configured to form a second transistor, wherein sizes of the first transistor and the second transistor are same, a deviation between an electrical parameter of the first transistor and an electrical parameter of the second transistor is below a preset threshold, and the first transistor and the second transistor belong to a cross coupling amplifying unit.

Provided is data receiving circuit, data receiving system and memory device. The data receiving circuit includes: first amplification circuit, configured to receive data signal, first reference signal and second reference signal, perform first comparison on the data signal and the first reference signal in response to sampling clock signal and output first signal pair, and perform second comparison on the data signal and the second reference signal and output second signal pair; second amplification circuit, configured to receive enable signal and feedback signal, selectively receive the first signal pair or the second signal pair as input signal pair based on the feedback signal during period in which the enable signal is at first level, receive the first signal pair during period in which the enable signal is at second level, amplify voltage difference of the first signal pair, and output first output signal and second output signal.

A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.

Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.