Thermosetting resin compositions useful for liquid compression molding encapsulation of a reconfigured wafer are provided. The so-encapsulated molded wafer offers improved resistance to warpage, compared to reconfigured wafers encapsulated with known encapsulation materials.

Thermosetting resin compositions useful for liquid compression molding encapsulation of a reconfigured wafer are provided. The so-encapsulated molded wafer offers improved resistance to warpage, compared to reconfigured wafers encapsulated with known encapsulation materials.

The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate, and a transistor, an anti-static wire, a first anti-static resistor and a first ground bonding pad on the base substrate, wherein a first terminal of the first anti-static resistor is electrically connected to a first end of the anti-static wire, a second terminal of the first anti-static resistor is electrically connected to the first ground bonding pad, and the first anti-static resistor is at a different layer from a layer at which the anti-static wire is located and a layer at which the first ground bonding pad is located, and is at a same layer as an active layer of the resistor.

An array substrate is provided, including a base substrate, a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode that are sequentially provided, and further including a first insulating layer, a second insulating layer, a third insulating layer, at least one first via, and at least one second via. Each first via penetrates through the third insulating layer, and in each pixel unit with plural chromatic color resists, each first via is between adjacent two chromatic color resists and filled by one of the adjacent two chromatic color resists. Each second via penetrates through the second insulating layer, the at least one second via is in one-to-one correspondence with the at least one first via, each second via is filled by a chromatic color resist having a same color as that of the chromatic color resist in the corresponding first via.

A display substrate and a method for manufacturing the same are provided. The display substrate includes a base substrate and a display element provided on the base substrate. The method includes steps of forming a first protection layer at at least one of outer peripheral sides of the base substrate, and removing the first protection layer before attaching a cover plate to the base substrate on which the display element is provided.

Disclosed are an array substrate and a manufacturing method thereof, a display panel, a display device and a pixel driving circuit. The array substrate includes: a base substrate; and a wiring layer and an effective light-emitting layer formed and stacked on the base substrate sequentially, wherein the wiring layer includes a first wiring and a second wiring, an orthographic projection of the first wiring on the base substrate overlaps an orthographic projection of the effective light-emitting layer on the base substrate to form a first overlapping area, an orthographic projection of the second wring on the base substrate overlaps the orthographic projection of the effective light-emitting layer on the base substrate to form a second overlapping area, and the first overlapping area and the second overlapping area are respectively located on both sides of a central line of the orthographic projection of the effective light-emitting layer on the base substrate.

Display substrate, method for manufacturing the same and display device are provided. The display substrate includes a base substrate comprising a hole region, an isolation region surrounding the hole region, and a display region surrounding the isolation region. At least one isolation pillar is provided within the isolation region, and each isolation pillar is arranged at a perimeter surrounding the hole region. A light-emitting layer covering the isolation pillar is provided in the display region and the isolation region, and the isolation pillar separates the light-emitting layer located between the hole region and the display region. The isolation pillar includes: a plurality of layers of metal patterns sequentially arranged in a stack on the base substrate; and an insulating film layer which is a layer stack covering the metal patterns and has a shape conforming to shapes of the metal patterns. The display substrate, the method for manufacturing the same, and the display device provided by the present disclosure enables reduced masks, reduced costs and simplified process.

A display substrate, a preparation method therefor, and a display apparatus. The preparation method comprises: providing a base substrate, a plurality of pixel drive circuits being formed on the base substrate, the plurality of pixel drive circuits comprising a first pixel drive circuit and a second pixel drive circuit; forming a first insulating layer on the base substrate; forming a first wiring layer on the first insulating layer, the first wiring layer comprising a first connecting wire, the first connecting wire being formed electrically connected to the first pixel drive circuit by means of the first insulating layer; forming and patterning a second insulating layer on the first wiring layer; forming a second wiring layer on a second insulating layer, the second wiring layer comprising a second connecting wire, the second connecting wire being formed electrically connected to the second pixel drive circuit by means of the first insulating layer and the second insulating layer; and forming and patterning a second insulating layer on the second wiring layer, the third insulating layer and the second insulating layer using the same reticle for the patterning process.

A method of manufacturing a parallel structure of semiconductor devices includes: disposing a semiconductor stack, which includes source/drain layers disposed vertically in sequence and channel layers therebetween, on a substrate; patterning the semiconductor stack into a predetermined shape to define an active region; forming gate stacks around at least part of peripheries of the channel layers; forming an isolation layer on peripheries of the active region and the gate stack; forming first to third conductive channels on a sidewall of the isolation layer; determining the pre-determined shape and a shape of the gate stacks, such that one of the source/drain layers on two sides of the channel layer passes through the isolation layer to contact the first conductive channel, while the other one passes through the isolation layer to contact the second conductive channel, and the gate stack passes through the isolation layer to contact the third conductive channel.

A method of manufacturing a parallel structure of semiconductor devices includes: disposing a semiconductor stack, which includes source/drain layers disposed vertically in sequence and channel layers therebetween, on a substrate; patterning the semiconductor stack into a predetermined shape to define an active region; forming gate stacks around at least part of peripheries of the channel layers; forming an isolation layer on peripheries of the active region and the gate stack; forming first to third conductive channels on a sidewall of the isolation layer; determining the pre-determined shape and a shape of the gate stacks, such that one of the source/drain layers on two sides of the channel layer passes through the isolation layer to contact the first conductive channel, while the other one passes through the isolation layer to contact the second conductive channel, and the gate stack passes through the isolation layer to contact the third conductive channel.