A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

The present disclosure provides a semiconductor structure, comprising a die/die stack attached on a substrate, a conductive top block covering a top surface of the die/die stack, and a plurality of ground wires conductively connect the conductive top block and to the substrate. The conductive top block, the plurality of ground wires, and the substrate form a Faraday cage to provide an electromagnetic interference shielding of the die/die stack.

A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages. Corresponding structures result from these methods.

A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.

A semiconductor device comprises a metallization layer, a passivation layer disposed above the metallization layer, a copper redistribution layer disposed on the passivation layer, a second passivation layer disposed on the copper redistribution layer, and a polyimide layer disposed over the second passivation layer. The polyimide layer and the second passivation layer include a continuous gap there-through that exposes a portion of the copper redistribution layer.

A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.