Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

A composite integrated circuit (IC) structure includes at least a first IC die in a stack with a second IC die. Each die has a device layer and metallization layers interconnected to transistors of the device layer and terminating at features. First features of the first IC die are primarily of a first composition with a first microstructure. Second features of the second IC die are primarily of a second composition or a second microstructure. A first one of the second features is in direct contact with one of the first features. The second composition has a thermal conductivity at least an order of magnitude lower than that of the first composition and first microstructure. The first composition may have a thermal conductivity at least 40 times that of the second composition or second microstructure.

A method of preparing a substrate for substrate bonding is provided. The method comprises: forming a recess in a substrate surface of the substrate, and forming a bondable dielectric layer on the substrate surface of the substrate. The bondable dielectric layer has a bonding surface on an opposite side of the bondable dielectric layer to the substrate surface, wherein the recess and the bondable dielectric layer define a dielectric cavity having a dielectric cavity volume. A plug is formed configured to make electrical contact to the substrate in the dielectric cavity volume. The plug has a plug volume which is less than the dielectric cavity volume, wherein the plug extends from the dielectric cavity beyond the bonding surface in a direction generally normal to the bonding surface. The plug is coined by compressing the substrate between opposing planar surfaces such that a contact surface of the plug is made co-planar with the bonding surface.

A method of preparing a substrate for substrate bonding is provided. The method comprises: forming a recess in a substrate surface of the substrate, and forming a bondable dielectric layer on the substrate surface of the substrate. The bondable dielectric layer has a bonding surface on an opposite side of the bondable dielectric layer to the substrate surface, wherein the recess and the bondable dielectric layer define a dielectric cavity having a dielectric cavity volume. A plug is formed configured to make electrical contact to the substrate in the dielectric cavity volume. The plug has a plug volume which is less than the dielectric cavity volume, wherein the plug extends from the dielectric cavity beyond the bonding surface in a direction generally normal to the bonding surface. The plug is coined by compressing the substrate between opposing planar surfaces such that a contact surface of the plug is made co-planar with the bonding surface.

A semiconductor device includes: a semiconductor chip having an element forming surface; an insulating layer formed on the element forming surface; a pad wiring layer including a first conductive layer formed on the insulating layer and containing a first conductive material and a second conductive layer formed on the first conductive layer and containing a second conductive material different from the first conductive material, wherein the second conductive layer includes an eaves portion protruding outward with respect to an end surface of the first conductive layer; a bonding member bonded to the pad wiring layer and supplying electric power to an element of the element forming surface; and a coating insulating film selectively formed on the insulating layer below the eaves portion, exposing an upper surface of the insulating layer to a peripheral region of the pad wiring layer, and covering the end surface of the first conductive layer.

A printed structure includes a destination substrate comprising two or more contact pads disposed on or in a surface of the destination substrate, a component disposed on the surface, and two or more electrically conductive connection posts. Each of the connection posts extends from a common side of the component. Each of the connection posts is in electrical and physical contact with one of the contact pads. The component is tilted with respect to the surface of the destination substrate. Each of the connection posts has a flat distal surface.

A printed structure includes a destination substrate comprising two or more contact pads disposed on or in a surface of the destination substrate, a component disposed on the surface, and two or more electrically conductive connection posts. Each of the connection posts extends from a common side of the component. Each of the connection posts is in electrical and physical contact with one of the contact pads. The component is tilted with respect to the surface of the destination substrate. Each of the connection posts has a flat distal surface.

A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.