A semiconductor package provided herein includes a first semiconductor die, a second semiconductor die and an insulating encapsulation. The second semiconductor die is stacked on the first semiconductor die. The insulating encapsulation laterally surrounds the first semiconductor die and the second semiconductor die in a one-piece form, and has a first sidewall and a second sidewall respectively adjacent to the first semiconductor die and the second semiconductor die. The first sidewall keeps a lateral distance from the second sidewall.

A micro-device structure includes a substrate having a substrate surface and a substrate contact disposed on or in the substrate surface, a cavity extending into the substrate from the substrate surface, a micro-device disposed in the cavity, the micro-device comprising a micro-device contact, a planarization layer disposed over at least a portion of the substrate, and an electrode disposed at least partially over or on the planarization layer and electrically connected to the micro-device contact.

Hydrophobic, tough, photoimageable, functionalized polyimide formulations have been discovered that can be UV cured and developed in cyclopentanone. The present invention formulations can be used as passivation and redistribution layers with patterning provided by photolithograph, for the redistribution of I/O pads on fan-out RDL applications. The curable polyimide formulations reduce stress on thin wafers, when compared to conventional polyimide formulations, and provide low modulus, hydrophobic solder mask. These materials can serve as protective layers in any applications in which a thin, flexible, and hydrophobic polymer is required, that also has high tensile strength and high elongation at break.

A conformal power delivery structure, a three-dimensional (3D) stacked die assembly, a system including the 3D stacked die assembly, and a method of forming the conformal power delivery structure. The power delivery structure includes a package substrate, a die adjacent to and electrically coupled to the package substrate; a first power plane adjacent the upper surface of the package substrate and electrically coupled thereto; a second power plane at least partially within recesses defined by the first power plane and having a lower surface that conforms with the upper surface of the first power plane; and a dielectric material between the first power plane and the second power plane.

Described herein is a method of forming wafer-level packages from a wafer. The method includes adhesively attaching front sides of first integrated circuits within the wafer to back sides of second integrated circuits such that pads on the front sides of the first integrated circuits and pads on front sides of the second integrated circuits are exposed. The method further includes forming a laser direct structuring (LDS) activatable layer over the front sides of the first integrated circuits and the second integrated circuits and over edges of the second integrated circuits, and forming desired patterns of structured areas within the LDS activatable layer. The method additionally includes metallizing the desired patterns of structured areas to form conductive areas within the LDS activatable layer.

A method comprises: providing a layer of curable adhesive material (4) on a substrate (2); forming a pattern of microstructures (321) on the layer of curable adhesive material (4); curing a first region (42) of the layer of curable adhesive material (4) at a first level and a second region (44) of the layer of curable adhesive material (4) at a second level greater than the first level; providing a solid circuit die (6) to directly attach to a major surface of the first region (42) of the layer of curable adhesive material (4); and further curing the first region (42) of the layer of curable adhesive material (4) to anchor the solid circuit die (6) on the first region (42) by forming an adhesive bond therebetween. The pattern of microstructures (321) may include one or more microchannels (321), the method further comprising forming one or more electrically conductive traces in the microchannels (321), in particular, by flow of a conductive particle containing liquid (8) by a capillary force and, optionally, under pressure. The at least one microchannel (321) may extend from the second region (44) to the first region (42) and have a portion beneath the solid circuit die (6). The solid circuit die (6) may have at least one edge disposed within a periphery of the first region (42) with a gap therebetween. The solid circuit die (6) may have at least one contact pad (72) on a bottom surface thereof, wherein the at least one contact pad (72) may be in direct contact with at least one of the electrically conductive traces in the microchannels (321). Forming the pattern of microstructures (321) may comprise contacting a major surface of a stamp (3) to the layer of curable adhesive material (4), the major surface having a pattern of raised features (32) thereon. The curable adhesive material (4) may be cured by an actinic light source such as an ultraviolet (UV) light source (7, 7′), wherein a mask may be provided to at least partially block the first region (42) of the layer of curable adhesive material (4) from the cure. The stamp (3) may be positioned in contact with the curable adhesive material (4) to replicate the pattern of raised features (32) to form the microstructures (321) while the curable adhesive material (4) is selectively cured by the actinic light source such as the ultraviolet (UV) light source (7). The first region (42) of the layer of curab

A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.

A coreless component carrier includes (a) a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure; and (b) a component embedded in the stack. At least one electrically insulating layer structure includes a reinforced layer structure, which is arranged at an outer main surface of the stack. Further described is a method for manufacturing such a coreless component carrier and preferably simultaneously a further coreless component carrier of the same type.

A method for forming a chip package structure is provided. The method includes forming a conductive pad over a carrier substrate. The method includes forming a substrate layer over the carrier substrate, wherein the conductive pad is embedded in the substrate layer, and the substrate layer includes fibers. The method includes forming a through hole in the substrate layer and exposing the conductive pad. The method includes forming a conductive pillar in the through hole. The method includes forming a recess in the substrate layer. The method includes disposing a chip in the recess. The method includes forming a molding layer in the recess. The method includes forming a redistribution structure over the substrate layer, the conductive pillar, the molding layer, and the chip. The method includes removing the carrier substrate.

A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.