A semiconductor package includes a first package substrate; a first semiconductor chip on the first package substrate; a first conductive connector on the first package substrate; and an interposer including a central portion on the first semiconductor chip and an outer portion having the first conductive connector attached thereto. The central portion of the interposer includes a bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate. A thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer.

A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.

A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

A power semiconductor device includes an insulating substrate on which a first conductor layer is arranged on one surface, a first conductor that is connected to the first conductor layer via a first connecting material, and a semiconductor element that is connected to the first conductor via a first connecting material. When viewed from a direction perpendicular to an electrode surface of the semiconductor element, the first conductor includes a peripheral portion formed larger than the semiconductor element. A first recess is formed in the peripheral portion so that a thickness of the first connecting material becomes thicker than other portions.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

A COF package includes a substrate and a chip, composite bumps on the chip are bonded to leads on the substrate. Each of the composite bumps includes a raising strip, a UBM layer and a bonding layer. A bonding rib is formed on the bonding layer because of the raising strip and the UBM layer, and the bonding rib on each of the composite bumps can be inserted into each of the leads and surface-contact with each of the leads to increase weld length and bonding strength between the bonding layer and the leads and further reduce a force required for bonding the chip to the substrate in a flip-chip bonding process.

A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.