An anisotropic conductive film (ACF), a bonding structure, and a display panel, and their fabrication methods are provided. The ACF includes a resin gel and a plurality of conductive particles dispersed in the resin gel. The plurality of conductive particles is aligned and connected, in response to an electric field, to form a conduction path in the resin gel. The bonding structure includes the anisotropic conductive film (ACF) sandwiched between first and second substrates. The display panel includes the bonding structure.

An anisotropic conductive film (ACF), a bonding structure, and a display panel, and their fabrication methods are provided. The ACF includes a resin gel and a plurality of conductive particles dispersed in the resin gel. The plurality of conductive particles is aligned and connected, in response to an electric field, to form a conduction path in the resin gel. The bonding structure includes the anisotropic conductive film (ACF) sandwiched between first and second substrates. The display panel includes the bonding structure.

A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.

A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

An electronic device comprising: an array substrate having a first electrode and a second electrode; a first connecting member arranged on the first electrode; a first LED chip mounted on the first connecting member; a second connecting member arranged on the second electrode and being thicker than the first connecting member; and a second LED chip mounted on the second connecting member. A distance from a reference surface of the array substrate to a top surface of the second connecting member is larger than a distance from the reference surface to a top surface of the first connecting member.

A semiconductor light emitting device includes: a light emitting element assembly including a semiconductor light emitting element including a support substrate and a light emitting semiconductor layer provided on the support substrate, and a light guide member adhered to the semiconductor light emitting element by an adhesive layer; and a first coating film formed of an inorganic material, which is a light reflector configured to cover a side surface of the light emitting element assembly.

A semiconductor package is disclosed. The semiconductor package includes a base structure, a first semiconductor chip over the base structure, a second semiconductor chip over the first semiconductor chip, an adhesive layer between the first semiconductor chip and the second semiconductor chip, and a molding layer covering the first semiconductor chip, the second semiconductor chip and the adhesive layer, and including an interposition portion interposed between the base structure and the first semiconductor chip.

A light-emitting device includes a light-emitting element having a first-type semiconductor layer, a second-type semiconductor layer, an active stack between the first-type semiconductor layer and the second-type semiconductor layer, a bottom surface, and a top surface. A first electrode is disposed on the bottom surface and electrically connected to the first-type semiconductor layer. A second electrode is disposed on the bottom surface and electrically connected to the second-type semiconductor layer. A supporting structure is disposed on the top surface. The supporting structure has a thickness and a maximum width. A ratio of the maximum width to the thickness is of 2˜150.