A MEMS device having a wafer-level package, is provided with: a stack of a first die and a second die, defining at least a first internal surface internal to the package and carrying at least an electrical contact pad, and at least a first external surface external to the package and defining a first outer face of the package; and a mold compound, at least in part coating the stack of the first and second dies and having a front surface defining at least part of a second outer face of the package, opposite to the first outer face. The MEMS device is further provided with: at least a vertical connection structure extending from the contact pad at the first internal surface towards the front surface of the mold compound; and at least an external connection element, electrically coupled to the vertical connection structure and exposed to the outside of the package, at the second outer face thereof.

A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.

A semiconductor chip for measuring a magnetic field. The semiconductor chip comprises a magnetic sensing element, and an electronic circuit. The magnetic sensing element is mounted on the electronic circuit. The magnetic sensing element is electrically connected with the electronic circuit. The electronic circuit is produced in a first technology and/or first material and the magnetic sensing element is produced in a second technology and/or second material different from the first technology/material.

An electronic device comprises a “waterproof” package including a substrate of an organic material permeable to humidity and/or moisture as well as one or more electronic components arranged on the substrate. The substrate comprises a barrier layer capable of countering penetration of humidity and/or moisture into the package through the organic material substrate.

A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.

Disclosed is a semiconductor package having a package-on-package (PoP) structure in which a signal region and a power region are formed separately. The semiconductor package includes a lower semiconductor package and an upper semiconductor package on the lower semiconductor package. The upper semiconductor package includes an upper package substrate, a memory chip on the upper package substrate, a wire that electrically connects the memory chip to the upper package substrate, a power connector on the upper semiconductor package, a signal connector on the bottom surface of the upper package substrate, and an upper package molding material.

A chip package structure includes a chip stack and a redistribution layer. The chip stack includes multiple chips stacked together, a molding layer encapsulating the multiple chips, and a vertical conductive element extending from a surface of the molding layer reach and coupled to the bonding pad. Each of the multiple chips includes a bonding pad not covered by the multiple chips. The redistribution layer is above the molding layer and includes a conductive layer coupled to the vertical conductive element, and an insulating layer over and partially exposing the conductive layer.

A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.