A wafer bonding method includes placing a first wafer on a first bonding framework including a plurality of outlet holes around a periphery of the first bonding framework. A second wafer is placed on a second bonding framework that includes a plurality of inlet holes around a periphery of the second bonding framework. The first bonding framework is in overlapping relation to the second bonding framework such that a gap exist between the first wafer and the second wafer. A gas stream is circulated through the gap between the first wafer and the second wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the first wafer and the second wafer.

A wafer bonding method includes placing a first wafer on a first bonding framework including a plurality of outlet holes around a periphery of the first bonding framework. A second wafer is placed on a second bonding framework that includes a plurality of inlet holes around a periphery of the second bonding framework. The first bonding framework is in overlapping relation to the second bonding framework such that a gap exist between the first wafer and the second wafer. A gas stream is circulated through the gap between the first wafer and the second wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the first wafer and the second wafer.

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.

An apparatus includes a transfer mechanism to transfer an electrically-actuatable element directly from a wafer tape to a transfer location on a circuit trace on a product substrate. The transfer mechanism includes one or more transfer wires. Two or more stabilizers disposed on either side of the one or more transfer wires. A needle actuator is connected to the one or more transfer wires and the two or more stabilizers to move the one or more transfer wires and the two or more stabilizers to a die transfer position.

An apparatus includes a transfer mechanism to transfer an electrically-actuatable element directly from a wafer tape to a transfer location on a circuit trace on a product substrate. The transfer mechanism includes one or more transfer wires. Two or more stabilizers disposed on either side of the one or more transfer wires. A needle actuator is connected to the one or more transfer wires and the two or more stabilizers to move the one or more transfer wires and the two or more stabilizers to a die transfer position.

The present technology relates to a semiconductor device, a manufacturing method, and a solid-state imaging device which are capable of suppressing a decrease in bonding strength and preventing a poor electrical connection or peeling when two substrates are bonded to each other. Provided is a semiconductor device, including: a first substrate including a first electrode including a metal; and a second substrate bonded to the first substrate and including a second electrode including a metal. An acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed. The present technology can be, for example, applied to a solid-state imaging device such as a CMOS image sensor.

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.

A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap.

A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap.

A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap.