Disclosed herein is an electrical connecting structure having nano-twins copper, including a first substrate having a first nano-twins copper layer and a second substrate having a second nano-twins copper layer. The first nano-twins copper layer includes a plurality of first nano-twins copper grains. The second nano-twins copper layer includes a plurality of second nano-twins copper grains. The first nano-twins copper layer is joined with the second nano-twins copper layer. At least a portion of the first nano-twins copper grains extend into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains extend into the first nano-twins copper layer.

Provided is a method for setting the conditions for heating a semiconductor chip during bonding of the semiconductor chip using an NCF, wherein a heating start temperature and a rate of temperature increase are set on the basis of a viscosity characteristic map that indicates changes in viscosity with respect to temperature of the NCF at various rates of temperature increase and a heating start temperature characteristic map that indicates changes in viscosity with respect to temperature of the NCF when the heating start temperature is changed at the same rate of temperature increase.

A display module and a method for manufacturing thereof are provided. The display module includes a substrate including a pad, a conduction film which is bonded to the substrate including the pad, wherein at least one of a surface of the conduction film and an inner portion of the conduction film is black color treated, and a display device mounted on the pad to which the conduction film is bonded.

A semiconductor package and a method of manufacturing the same, and an imaging apparatus are provided. The method includes preparing a substrate having a first connection region and a sensor chip having a second connection region. A first bonding layer including multi-layer nano low-melting-point metal materials with different melting point gradients is provided on the first connection region. A second bonding layer including multi-layer nano low-melting-point metal materials with different melting point gradients is provided on the second connection region. The substrate and the sensor chip are overlapped to align and tightly compress the first and second bonding layers, to obtain a composite structure. The composite structure is treated at a temperature of 30 to 180° C., under a pressure of 1 to 8 MPa, and with an ultrasonic of 10 to 30 kHz to form the first and second bonding layers into a eutectic.

A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles 5 (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip 3 and a substrate 2 to be bonded to the semiconductor chip 3, and the metal particles 5 are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles 5, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip 3 and/or the surface of the substrate 2.

A display module and a method for manufacturing thereof are provided. The display module includes a substrate including a pad, a conduction film which is bonded to the substrate including the pad, wherein at least one of a surface of the conduction film and an inner portion of the conduction film is black color treated, and a display device mounted on the pad to which the conduction film is bonded.

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200° C. and in some embodiments at about 150° C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

The present invention discloses flip-chip bonding method using an anisotropic adhesive polymer. The method includes applying an adhesive polymer solution containing metal particles dispersed therein onto a circuit substrate to form an adhesive polymer layer such that the adhesive polymer layer covers the metal particles; drying the adhesive polymer layer; and positioning an electronic element to be electrically connected to the circuit substrate on the dried adhesive polymer layer and causing dewetting of the polymer from the metal particles.

Disclosed herein is a method of forming an electrical connecting structure having nano-twins copper. The method includes the steps of (i) forming a first nano-twins copper layer including a plurality of nano-twins copper grains; (ii) forming a second nano-twins copper layer including a plurality of nano-twins copper grains; and (iii) joining a surface of the first nano-twins copper layer with a surface of the second nano-twins copper layer, such that at least a portion of the first nano-twins copper grains grow into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains grow into the first nano-twins copper layer. An electrical connecting structure having nano-twins copper is provided as well.

The invention relates to a positioning device for positioning a substrate, in particular a wafer, comprising: a process chamber; a base body; a carrier element which comprises a support for supporting the substrate, the carrier element being arranged above the base body and formed movable in terms of distance from the base body; and a holder for an additional substrate, in particular an additional wafer or a mask, the holder being arranged opposite the carrier element; wherein there is, between the base body and the carrier element, a sealed-off cavity to which a pressure, in particular a negative pressure, can be applied so as to prevent undesired movement of the carrier element as a result of the action of an external force.