Patent classifications
H01L2224/83127
Conductive connecting member and manufacturing method of same
A conductive connecting member formed on a bonded face of an electrode terminal of a semiconductor or an electrode terminal of a circuit board, the conductive connecting member comprising a porous body formed in such manner that a conductive paste containing metal fine particles (P) having mean primary particle diameter from 10 to 500 nm and an organic solvent (S), or a conductive paste containing the metal fine particles (P) and an organic dispersion medium (D) comprising the organic solvent (S) and an organic binder (R) is heating-treated so as for the metal fine particles (P) to be bonded, the porous body being formed by bonded metal fine particles (P) having mean primary particle diameter from 10 to 500 nm, a porosity thereof being from 5 to 35 volume %, and mean pore diameter being from 1 to 200 nm.
Electronic packages with pre-defined via patterns and methods of making and using the same
An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer disposed on at least a portion of the metal built-up layer. Moreover, the electronic package includes a second conductive layer disposed on the first conductive layer, where the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.
Underfill material, laminated sheet and method for producing semiconductor device
An underfill material having sufficient curing reactivity, and capable of achieving a small change in viscosity and good electrical connection even when loaded with thermal history, a laminated sheet including the underfill material, and a method for manufacturing a semiconductor device. The underfill material has a melt viscosity at 150 C. before heating treatment of 50 Pa.Math.s or more and 3,000 Pa.Math.s or less, a viscosity change rate of 500% or less, at 150 C. as a result of the heating treatment, and a reaction rate represented by {(QtQh)/Qt}100% of 90% or more, where Qt is a total calorific value in a process of temperature rise from 50 C. to 300 C. and Qh is a total calorific value in a process of temperature rise from 50 C. to 300 C. after heating at 175 C. for 2 hours in a DSC measurement.
METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY
A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.
METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY
A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.
Method and apparatus for a seal ring structure
A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.
Underfill Material, Laminated Sheet and Method for Producing Semiconductor Device
An underfill material having sufficient curing reactivity, and capable of achieving a small change in viscosity and good electrical connection even when loaded with thermal history, a laminated sheet including the underfill material, and a method for manufacturing a semiconductor device. The underfill material has a melt viscosity at 150 C. before heating treatment of 50 Pa.Math.s or more and 3,000 Pa.Math.s or less, a viscosity change rate of 500% or less, at 150 C. as a result of the heating treatment, and a reaction rate represented by {(QtQh)/Qt}100% of 90% or more, where Qt is a total calorific value in a process of temperature rise from 50 C. to 300 C. and Qh is a total calorific value in a process of temperature rise from 50 C. to 300 C. after heating at 175 C. for 2 hours in a DSC measurement.
Offset alignment and repair in micro device transfer
This invention relates to the process of correcting misalignment and filling voids after a microdevice transfer process. The process involves transfer heads, measurement of offset and misalignment in horizontal, vertical, and rotational errors. An execution of the new offset vector for the next transfer corrects the alignment.