Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided.

Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided.

A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

Provided is a package structure including a photonic die, an electronic die, a conductive layer, a circuit substrate, and an underfill. The electronic die is bonded on a front side of the photonic die. The conductive layer is disposed on a back side of the photonic die. The conductive layer includes a plurality of conductive pads and a dam structure between the conductive pads and a first sidewall of the photonic die. The circuit substrate is bonded on the back side of the photonic die through a plurality of connectors and the conductive pads. The underfill laterally encapsulates the connectors, the conductive pads, and the dam structure. The underfill at the first sidewall of the photonic die has a first height, the underfill at a second sidewall of the photonic die has a second height, and the first height is lower than the second height.

Provided is a package structure including a photonic die, an electronic die, a conductive layer, a circuit substrate, and an underfill. The electronic die is bonded on a front side of the photonic die. The conductive layer is disposed on a back side of the photonic die. The conductive layer includes a plurality of conductive pads and a dam structure between the conductive pads and a first sidewall of the photonic die. The circuit substrate is bonded on the back side of the photonic die through a plurality of connectors and the conductive pads. The underfill laterally encapsulates the connectors, the conductive pads, and the dam structure. The underfill at the first sidewall of the photonic die has a first height, the underfill at a second sidewall of the photonic die has a second height, and the first height is lower than the second height.

A semiconductor package of an embodiment includes a wiring substrate, a semiconductor chip provided on an upper surface of the wiring substrate, a sealing resin covering surfaces of the wiring substrate and the semiconductor chip, an infrared reflection layer containing any of aluminum, aluminum oxide, and titanium oxide, and an external terminal provided on a lower surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal. The infrared reflection layer is provided to the sealing resin on an upper side of a surface of the semiconductor chip on a side opposite to an upper surface of the wiring substrate.

A semiconductor package of an embodiment includes a wiring substrate, a semiconductor chip provided on an upper surface of the wiring substrate, a sealing resin covering surfaces of the wiring substrate and the semiconductor chip, an infrared reflection layer containing any of aluminum, aluminum oxide, and titanium oxide, and an external terminal provided on a lower surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal. The infrared reflection layer is provided to the sealing resin on an upper side of a surface of the semiconductor chip on a side opposite to an upper surface of the wiring substrate.

An electronic-component-mounted module has an electronic component, a first silver-sintered bonding layer bonded on one surface of the electronic component, a circuit layer made of copper or copper alloy and bonded on the first silver-sintered bonding layer, and a ceramic substrate board bonded on the circuit layer, and further has an insulation circuit substrate board with smaller linear expansion coefficient than the electronic component, a second silver-sintered bonding layer bonded on the other surface of the electronic component, and a lead frame with smaller linear expansion coefficient than the electronic component bonded on the second silver-sintered bonding layer; and a difference in the linear expansion coefficient between the insulation circuit substrate board and the lead frame is not more than 5 ppm/ C.

An electronic-component-mounted module has an electronic component, a first silver-sintered bonding layer bonded on one surface of the electronic component, a circuit layer made of copper or copper alloy and bonded on the first silver-sintered bonding layer, and a ceramic substrate board bonded on the circuit layer, and further has an insulation circuit substrate board with smaller linear expansion coefficient than the electronic component, a second silver-sintered bonding layer bonded on the other surface of the electronic component, and a lead frame with smaller linear expansion coefficient than the electronic component bonded on the second silver-sintered bonding layer; and a difference in the linear expansion coefficient between the insulation circuit substrate board and the lead frame is not more than 5 ppm/ C.