A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness.

A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness.

In a described example, an apparatus includes: a semiconductor die with a component on a device side surface; a die seal surrounding the component on the device side surface; a package substrate having bond pads on a die side surface; a package substrate seal formed on the die side surface of the package substrate corresponding to the die seal on the semiconductor die; the semiconductor die flip chip mounted on the bond pads of the package substrate with solder joints connecting post connects on the semiconductor die to the bond pads of the package substrate; a mold compound seal formed by the die seal and the package substrate seal; and mold compound covering a portion of the semiconductor die, a portion of the die side of the package substrate, and contacting the mold compound seal, the mold compound spaced from the component.

In a described example, an apparatus includes: a semiconductor die with a component on a device side surface; a die seal surrounding the component on the device side surface; a package substrate having bond pads on a die side surface; a package substrate seal formed on the die side surface of the package substrate corresponding to the die seal on the semiconductor die; the semiconductor die flip chip mounted on the bond pads of the package substrate with solder joints connecting post connects on the semiconductor die to the bond pads of the package substrate; a mold compound seal formed by the die seal and the package substrate seal; and mold compound covering a portion of the semiconductor die, a portion of the die side of the package substrate, and contacting the mold compound seal, the mold compound spaced from the component.

Disclosed herein is a ceramic particle comprising a core substrate chosen from yttria-stabilized zirconia, partially stabilized zirconia, zirconium oxide, aluminum nitride, silicon nitride, silicon carbide, and cerium oxide, and a conformal coating of a sintering aid film having a thickness of less than three nanometers and covering the core substrate, and methods for producing the ceramic particle.

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

A lid body includes a base containing an alloy of iron and nickel, a first film positioned on a lower surface of the base and containing nickel, and a second film positioned on a lower surface of the first film and containing copper. During welding of the lid body, penetration of crystal grain boundaries of the base by Cu of the second film is reduced by the first film. Therefore, occurrence of cracks in the base is reduced and thus a package with high airtightness can be formed.

A lid body includes a base containing an alloy of iron and nickel, a first film positioned on a lower surface of the base and containing nickel, and a second film positioned on a lower surface of the first film and containing copper. During welding of the lid body, penetration of crystal grain boundaries of the base by Cu of the second film is reduced by the first film. Therefore, occurrence of cracks in the base is reduced and thus a package with high airtightness can be formed.

A package has a cavity to be sealed by a lid. The package includes a heat sink having a coefficient of thermal expansion of 9 ppm/° C. or more and 15 ppm/° C. or less from 25 ° C. to 100 ° C. and a frame disposed on the heat sink, made of ceramics, and surrounding the cavity in plan view. An outer edge of the frame includes a first linear portion extending along a first direction, a second linear portion extending along a second direction orthogonal to the first direction, and a chamfer connecting the first linear portion and the second linear portion in plan view.